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CD74AC74M96G4 PDF预览

CD74AC74M96G4

更新时间: 2024-11-05 11:06:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器锁存器
页数 文件大小 规格书
8页 38K
描述
具有设置和复位端的双路正边沿触发式 D 型触发器 | D | 14 | -55 to 125

CD74AC74M96G4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.21系列:AC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:90000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:3.3/5 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:14 ns
传播延迟(tpd):125 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.91 mm最小 fmax:110 MHz
Base Number Matches:1

CD74AC74M96G4 数据手册

 浏览型号CD74AC74M96G4的Datasheet PDF文件第2页浏览型号CD74AC74M96G4的Datasheet PDF文件第3页浏览型号CD74AC74M96G4的Datasheet PDF文件第4页浏览型号CD74AC74M96G4的Datasheet PDF文件第5页浏览型号CD74AC74M96G4的Datasheet PDF文件第6页浏览型号CD74AC74M96G4的Datasheet PDF文件第7页 
CD74AC74,  
CD74ACT74  
Data sheet acquired from Harris Semiconductor  
SCHS231  
Dual D-Type Flip-Flop with Set and Reset  
Positive-Edge-Triggered  
September 1998  
Features  
Description  
[ /Title  
(CD74  
AC74,  
CD74  
ACT74  
)
/Sub-  
ject  
(Dual  
D-  
• Buffered Inputs  
The Harris CD74AC74 and CD74ACT74 dual D-type, posi-  
tive edge triggered flip-flops use the Harris ADVANCED  
CMOS technology. These flip-flops have independent DATA,  
SET, RESET, and CLOCK inputs and Q and Q outputs. The  
logic level present at the data input is transferred to the out-  
put during the positive going transition of the clock pulse.  
SET and RESET are independent of the clock and are  
accomplished by a low level at the appropriate input.  
• Typical Propagation Delay (AC00)  
o
- 4.9ns at V  
= 5V, T = 25 C, C = 50pF  
A L  
CC  
• Exceeds 2kV ESD Protection MIL-STD-883, Method  
3015  
• SCR-Lachup-Resistant CMOS Process and Circuit  
Design  
Ordering Information  
• Speed of Bipolar FAST™/AS/S with Significantly  
Reduced Power Consumption  
PART  
NUMBER  
TEMP.  
RANGE ( C)  
PKG.  
NO.  
o
PACKAGE  
Type  
Flip-  
Flop  
• Balanced Propagation Delays  
CD74AC74E  
CD74ACT74E  
CD74AC74EX  
CD74ACT74EX  
CD74AC74M  
CD74ACT74M  
NOTES:  
0 to 70, -40 to 85  
-55 to 125  
14 Ld PDIP  
E14.3  
E14.3  
E14.3  
E14.3  
M14.15  
M14.15  
• AC Types Feature 1.5V to 5.5V Operation and  
Balanced Noise Immunity at 30% of the Supply  
0 to 70, -40 to 85  
-55 to 125  
14 Ld PDIP  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
with  
±24mA Output Drive Current  
- Fanout to 15 FAST™ ICs  
Setand  
Reset  
Posi-  
tive-  
Edge-  
Trig-  
gered)  
/Autho  
r ()  
/Key-  
words  
(Har-  
ris  
0 to 70, -40 to 85  
-55 to 125  
- Drives 50Transmission Lines  
0 to 70, -40 to 85  
-55 to 125  
0 to 70, -40 to 85  
-55 to 125  
0 to 70, -40 to 85  
-55 to 125  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer and die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or Harris  
customer service for ordering information.  
Semi-  
con-  
Pinout  
ductor,  
Advan  
ced  
CD74AC74, CD74ACT74  
(PDIP, SOIC)  
TOP VIEW  
CMOS  
,Harris  
Semi-  
con-  
ductor,  
Advan  
1R  
1D  
1
2
3
4
5
6
7
14 V  
CC  
13 2R  
12 2D  
11 2CP  
10 2S  
1CP  
1S  
1Q  
1Q  
9
8
2Q  
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a Trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1998  
File Number 1881.1  
1

CD74AC74M96G4 替代型号

型号 品牌 替代类型 描述 数据表
CD74AC74MG4 TI

完全替代

Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset 14-SOIC -55 to 125
CD74AC74ME4 TI

完全替代

Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset 14-SOIC -55 to 125
CD74AC74M96 TI

类似代替

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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