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CD74AC74MG4 PDF预览

CD74AC74MG4

更新时间： 2024-11-04 15:46:23
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
14页 669K
描述
D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14

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CD74AC74MG4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65系列：AC
JESD-30 代码：R-PDSO-G14长度：8.65 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：125 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.5 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：110 MHzBase Number Matches：1

CD74AC74MG4 数据手册

 浏览型号CD74AC74MG4的Datasheet PDF文件第2页浏览型号CD74AC74MG4的Datasheet PDF文件第3页浏览型号CD74AC74MG4的Datasheet PDF文件第4页浏览型号CD74AC74MG4的Datasheet PDF文件第5页浏览型号CD74AC74MG4的Datasheet PDF文件第6页浏览型号CD74AC74MG4的Datasheet PDF文件第7页 
CD54AC74, CD74AC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002  
CD54AC74 . . . F PACKAGE  
CD74AC74 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Balanced Propagation Delays  
1CLK  
1PRE  
1Q  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
2CLK  
10 2PRE  
9
8
1Q  
2Q  
2Q  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
GND  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description/ordering information  
The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
SOIC – M  
CDIP – F  
Tube  
Tube  
CD74AC74E  
CD74AC74M  
CD74AC74E  
–55°C to 125°C  
AC74M  
Tape and reel CD74AC74M96  
Tube CD54AC74F3A  
CD54AC74F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
‡
‡
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
‡
This configuration is nonstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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