Datasheet > CD40103BMS

CD40103BMS

更新时间： 2024-01-17 10:35:49

品牌	Logo	应用领域
英特矽尔 - INTERSIL		计数器
页数	文件大小	规格书
13页	169K
描述
CMOS 8-Stage Presettable Synchronous Down Counters

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中文翻译

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数据手册

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CD40103BMS 数据手册

CD40102BMS

CD40103BMS

CMOS 8-Stage Presettable

Synchronous Down Counters

December 1992

Features

Description

• High Voltage Type (20V Rating)

• CD40102BMS: 2-Decade BCD Type

• CD40103BMS: 8-Bit Binary Type

• Synchronous or Asynchronous Preset

CD40102BMS and CD40103BMS consist of an 8-stage syn-

chronous down counter with a single output which is active

when the internal count is zero. The CD40102BMS is conﬁg-

ured as two cascaded 4-bit BCD counters, and the

CD40103BMS contains a single 8-bit binary counter. Each

type has control inputs for enabling or disabling the clock, for

clearing the counter to its maximum count, and for presetting

the counter either synchronously or asynchronously. All con-

trol inputs and the CARRY-OUT/ZERO-DETECT output are

active-low logic.

• Medium Speed Operation

- fCL = 3.6MHz (Typ) at 10V

• Cascadable

• 100% Tested for Quiescent Current at 20V

In normal operation, the counter is decremented by one

count on each positive transition of the CLOCK. Counting is

inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)

inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD)

output goes low when the count reaches zero if the CI/CE

input is low, and remains low for one full clock period.

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

When the SYNCHRONOUS PRESET-ENABLE (SPE) input

is low, data at the JAM input is clocked into the counter on

the next positive clock transition regardless of the state of

the CI/CE input. When the ASYNCHRONOUS PRESET-

ENABLE (APE) input is low, data at the JAM inputs is asyn-

chronously forced into the counter regardless of the state of

the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 repre-

sent two 4-bit BCD words for the CD40102BMS and a single

8-bit binary word for the CD40103BMS.

- 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

When the CLEAR (CLR) input is low, the counter is asyn-

chronously cleared to its maximum count (99₁₀for the

CD40102BMS and 255₁₀for the CD40103BMS) regardless

of the state of any other input. The precedence relationship

between control inputs is indicated in the truth table.

Applications

• Divide-By- “N” Counters

• Programmable Times

• Interrupt Timers

If all control inputs except CI/CE are high at the time of zero

count, the counters will jump to the maximum count, giving a

counting sequence of 100 or 256 clock pulses long.

• Cycle/Program Counter

This causes the CO/ZD output to go low to enable the clock

on each succeeding clock pulse.

Pinout

CD40102BMS, CD40130BMS

The CD40102BMS and CD40103BMS may be cascaded

using the CI/CE input and the CO/ZD output, in either a syn-

chronous or ripple mode as shown in Figures 16 and 17.

TOP VIEW

CLOCK

CLEAR

16 VDD

The CD40102MS and CD40103BMS are supplied in these

16-lead outline packages:

SYNCHRONOUS

PRESET ENABLE

CARRY OUT/

CARRY IN/

COUNTER ENABLE

ZERO DETECT

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

*CD40102B Only

*H4W †H4X

13 J7

12 J6

11 J5

10 J4

*H1L

H6W

†H1F

†CD40130B Only

ASYNCHRONOUS

PRESET ENABLE

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3351

7-1294

12 3 4 5 6 7...13

中文翻译

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与CD40103BMS相关器件

型号	品牌	获取价格	描述	数据表
CD40103BNSR	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BNSRE4	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BPW	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BPWE4	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BPWG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, PDSO16, GR
CD40103BPWR	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BPWRE4	TI	获取价格	CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
CD40103BPWRG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, PDSO16, GR
CD40104BEX98	RENESAS	获取价格	Shift Register, 4-Bit, CMOS, PDIP16
CD40104BMS	INTERSIL	获取价格	CMOS 4-Bit Bidirectional Universal Shift Register

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