CD40104BMS,
CD40194BMS
CMOS 4-Bit Bidirectional
Universal Shift Register
December 1992
CD40104BMS
TOP VIEW
Features
• High Voltage Type (20V Rating)
Pinouts
• Medium Speed fCL = 12MHz (typ.) at VDD = 10V
• Fully Static Operation
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTPUT ENABLE
VDD
SHIFT RIGHT IN
Q0
D0
Q1
• Synchronous Parallel or Serial Operation
• Three State Outputs (CD40104BMS)
• Asynchronous Master Reset (CD40194BMS)
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
D1
Q2
D2
Q3
D3
SHIFT LEVEL IN
VSS
CLOCK
SELECT 1
SELECT 0
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD40194BMS
TOP VIEW
Applications
• Arithmetic Unit Bus Registers
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RESET
VDD
SHIFT RIGHT IN
Q0
• Serial/Parallel Conversions
D0
Q1
• General Purpose Register for Bus Organized Systems
• General Purpose Registers
D1
Q2
D2
Q3
D3
SHIFT LEVEL IN
VSS
CLOCK
SELECT 1
SELECT 0
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
Functional Diagrams
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
CD40104BMS
OUTPUT ENABLE
1
3
4
15
Q0
14
Q1
13
Q2
12
Q3
D0
D1
5
D2
D3
6
7
SHIFT LEFT IN
2
SHIFT RIGHT IN
S0
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
9
10
MODE SELECT
S1
VDD = 16
VSS = 8
11
CLOCK
CD40194BMS
RESET
1
3
4
15
14
13
12
D0
Q0
Q1
Q2
Q3
D1
5
D2
D3
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
6
7
SHIFT LEFT IN
2
Braze Seal DIP
Frit Seal DIP
*HNX, †H4W
*H1L, †HIF
H6W
SHIFT RIGHT IN
S0
9
10
MODE SELECT
S1
VDD = 16
VSS = 8
Ceramic Flatpack
* CD40104B Only
11
CLOCK
†CD40194B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3352
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1307
5秒后页面跳转
SL74HC10N：高性能三输入与非门解析
AIC1781A 电池充电控制器深度解析
Pickering新高压舌簧继电器亮相汽车测试博览会
采用MCU+MPU双处理器架构实现的创新应用设计探索
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
