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CD40105BFMSR PDF预览

CD40105BFMSR

更新时间： 2024-09-09 14:41:23
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟先进先出芯片输入元件内存集成电路
页数 文件大小 规格书
10页 115K
描述
16X4 OTHER FIFO, CDIP16, FRIT SEALED, CERAMIC, DIP-16

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CD40105BFMSR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.26其他特性：INPUT AC PARAMETRIC VALUES NOT FROM POST RADIATION MEASUREMENT; REGISTER BASED
最大时钟频率 (fCLK)：1.5 MHz周期时间：900.9 ns
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：37.4 mm内存密度：64 bit
内存集成电路类型：OTHER FIFO内存宽度：4
功能数量：1端子数量：16
字数：16 words字数代码：16
工作模式：SYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：16X4
可输出：YES封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V认证状态：Not Qualified
筛选级别：38535V;38534K;883S座面最大高度：6.35 mm
子类别：FIFOs标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

CD40105BFMSR 数据手册

 浏览型号CD40105BFMSR的Datasheet PDF文件第2页浏览型号CD40105BFMSR的Datasheet PDF文件第3页浏览型号CD40105BFMSR的Datasheet PDF文件第4页浏览型号CD40105BFMSR的Datasheet PDF文件第5页浏览型号CD40105BFMSR的Datasheet PDF文件第6页浏览型号CD40105BFMSR的Datasheet PDF文件第7页 
CD40105BMS  
CMOS FIFO Register  
December 1992  
Features  
Description  
• 4 Bits x 16 Words  
CD40105BMS is a low-power first-in-first-out (FIFO) “elastic”  
storage register that can store 16 4-bit words. It is capable of  
handling input and output data at different shifting rates. This  
feature makes it particularly useful as a buffer between asyn-  
chronous systems.  
• High Voltage Type (20V Rating)  
• Independent Asynchronous Inputs and Outputs  
• 3-State Outputs  
• Expandable in Either Direction  
• Status Indicators on Input and Output  
• Reset Capability  
Each word position in the register is clocked by a control flip-  
flop, which stores a marker bit. A “1” signifies that the posi-  
tion’s data is filled and a “0” denotes a vacancy in that posi-  
tion. The control flip-flop detects the state of the preceding  
flip-flop and communicates its own status to the succeeding  
flip-flop. When a control flip-flop is in the “0” state and sees a  
“1” in the preceding flip-flop, it generates a clock pulse that  
transfers data from the preceding four data latches into its  
own four data latches and resets the preceding flip-flop to  
“0”. The first and last control flip-flops have buffered outputs.  
Since all empty locations “bubble” automatically to the input  
end, and all valid data ripple through to the output end, the  
status of the first control flip-flop (DATA-IN READY) indicates  
if the FIFO is full, and the status of the last flip-flop (DATA-  
OUT READY) indicates if the FIFO contains data. As the  
earliest data are removed from the bottom of the data stack  
(the output end), all data entered later will automatically  
propagate (ripple) toward the output.  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Loading Data - Data can be entered whenever the DATA-IN  
READY (DIR) flag is high, by a low to high transition on the  
SHIFT-IN (SI) input. This input must go low momentarily  
before the next word is accepted by the FIFO. The DIR flag  
will go low momentarily, until that data have been transferred  
to the second location. The flag will remain low when all 16-  
word locations are filled with valid data, and further pulses  
on the SI input will be ignored until DIR goes high.  
Applications  
• Bit Rate Smoothing  
• CPU/Terminal Buffering  
• Data Communications  
• Peripheral Buffering  
• Line Printer Input Buffers  
• Auto Dialers  
Continued on next page  
• CRT Buffer Memories  
• Radar Data Acquisition  
Pinout  
Functional Diagram  
CD40105BMS  
TOP VIEW  
3-STATE  
CONTROL  
3 - STATE  
1
1
2
3
4
5
6
7
8
16 VDD  
CONTROL  
4
5
6
7
13  
12  
11  
10  
Q0  
Q1  
Q2  
Q3  
D0  
D1  
D2  
D3  
DIR  
15  
14  
SO  
SI  
D0  
DOR  
13 Q0  
12 Q1  
11 Q2  
10 Q3  
D1  
DATA-OUT  
READY  
DATA-IN  
READY  
3
14  
2
SHIFT IN  
D2  
15  
SHIFT OUT  
D3  
9
9
VSS  
VDD = 16  
VSS = 8  
MR  
MASTER  
RESET  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3353  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1317  
1234567...10

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