Datasheet > CD40105BFMSR

CD40105BFMSR

更新时间： 2024-11-04 14:41:23

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟先进先出芯片输入元件内存集成电路
页数	文件大小	规格书
10页	115K
描述
16X4 OTHER FIFO, CDIP16, FRIT SEALED, CERAMIC, DIP-16

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技术参数
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CD40105BFMSR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP16,.3
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.26	其他特性：	INPUT AC PARAMETRIC VALUES NOT FROM POST RADIATION MEASUREMENT; REGISTER BASED
最大时钟频率 (fCLK)：	1.5 MHz	周期时间：	900.9 ns
JESD-30 代码：	R-GDIP-T16	JESD-609代码：	e0
长度：	37.4 mm	内存密度：	64 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	4
功能数量：	1	端子数量：	16
字数：	16 words	字数代码：	16
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16X4
可输出：	YES	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5/15 V	认证状态：	Not Qualified
筛选级别：	38535V;38534K;883S	座面最大高度：	6.35 mm
子类别：	FIFOs	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

CD40105BFMSR 数据手册

CD40105BMS

CMOS FIFO Register

December 1992

Features

Description

• 4 Bits x 16 Words

CD40105BMS is a low-power ﬁrst-in-ﬁrst-out (FIFO) “elastic”

storage register that can store 16 4-bit words. It is capable of

handling input and output data at different shifting rates. This

feature makes it particularly useful as a buffer between asyn-

chronous systems.

• High Voltage Type (20V Rating)

• Independent Asynchronous Inputs and Outputs

• 3-State Outputs

• Expandable in Either Direction

• Status Indicators on Input and Output

• Reset Capability

Each word position in the register is clocked by a control ﬂip-

ﬂop, which stores a marker bit. A “1” signiﬁes that the posi-

tion’s data is ﬁlled and a “0” denotes a vacancy in that posi-

tion. The control ﬂip-ﬂop detects the state of the preceding

ﬂip-ﬂop and communicates its own status to the succeeding

ﬂip-ﬂop. When a control ﬂip-ﬂop is in the “0” state and sees a

“1” in the preceding ﬂip-ﬂop, it generates a clock pulse that

transfers data from the preceding four data latches into its

own four data latches and resets the preceding ﬂip-ﬂop to

“0”. The ﬁrst and last control ﬂip-ﬂops have buffered outputs.

Since all empty locations “bubble” automatically to the input

end, and all valid data ripple through to the output end, the

status of the ﬁrst control ﬂip-ﬂop (DATA-IN READY) indicates

if the FIFO is full, and the status of the last ﬂip-ﬂop (DATA-

OUT READY) indicates if the FIFO contains data. As the

earliest data are removed from the bottom of the data stack

(the output end), all data entered later will automatically

propagate (ripple) toward the output.

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Loading Data - Data can be entered whenever the DATA-IN

READY (DIR) ﬂag is high, by a low to high transition on the

SHIFT-IN (SI) input. This input must go low momentarily

before the next word is accepted by the FIFO. The DIR ﬂag

will go low momentarily, until that data have been transferred

to the second location. The ﬂag will remain low when all 16-

word locations are ﬁlled with valid data, and further pulses

on the SI input will be ignored until DIR goes high.

Applications

• Bit Rate Smoothing

• CPU/Terminal Buffering

• Data Communications

• Peripheral Buffering

• Line Printer Input Buffers

• Auto Dialers

Continued on next page

• CRT Buffer Memories

• Radar Data Acquisition

Pinout

Functional Diagram

CD40105BMS

TOP VIEW

3-STATE

CONTROL

3 - STATE

16 VDD

CONTROL

DIR

DOR

13 Q0

12 Q1

11 Q2

10 Q3

DATA-OUT

READY

DATA-IN

READY

SHIFT IN

SHIFT OUT

VSS

VDD = 16

VSS = 8

MASTER

RESET

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3353

7-1317

12 3 4 5 6 7...10

中文翻译

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与CD40105BFMSR相关器件

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CD40105BK3	ROCHESTER	获取价格	16X4 OTHER FIFO, PDSO16
CD40105BKMSR	ETC	获取价格	x4 Asynchronous FIFO
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CD40106	NSC	获取价格	Hex Schmitt Trigger
CD40106	TI	获取价格	CMOS HEX SCHMITT TRIGGERS
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CD40106	HGSEMI	获取价格	六路反相施密特触发器
CD40106_12	UTC	获取价格	HEX SCHMITT TRIGGERS
CD40106B	TI	获取价格	CMOS HEX SCHMITT TRIGGERS

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