Datasheet > CD40106

CD40106

更新时间： 2024-11-03 22:56:43

品牌	Logo	应用领域
英特矽尔 - INTERSIL		触发器
页数	文件大小	规格书
9页	78K
描述
CMOS Hex Schmitt Triggers

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数据手册

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CD40106 数据手册

CD40106BMS

CMOS Hex Schmitt Triggers

December 1992

Features

Pinout

CD40106BMS

TOP VIEW

• High Voltage Type (20V Rating)

• Schmitt Trigger Action with No External Components

• Hysteresis Voltage (Typ.)

- 0.9V at VDD = 5V

G = A

14 VDD

13 F

2.3V at VDD = 10V

12 L = F

11 E

- 3.5V at VDD = 15V

H = B

• Noise Immunity Greater than 50%

• No Limit on Input Rise and Fall Times

• Low VDD to VSS Current During Slow Input Ramp

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

10 K = E

I = C

VSS

J = D

• Maximum Input Current of 1µA at 18V Over Full Pack- Functional Diagram

age Temperature Range; 100nA at 18V and +25^oC

• Standardized Symmetrical Output Characteristics

G = A

H = B

I = C

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Applications

• Wave and Pulse Shapers

• High Noise Environment Systems

• Monostable Multivibrators

• Astable Multivibrators

J = D

K = E

L = F

Description

CD40106BMS consists of six Schmitt trigger circuits. Each

circuit functions as an inverter with Schmitt trigger action on

the input. The trigger switches at different points for positive

and negative going signals. The difference between the

positive going voltage (VP) and the negative going voltage

(VN) is deﬁned as hysteresis voltage (VH) (see Figure 17).

Logic Diagram

1 (3, 5, 9, 11, 13)

2 (4, 6, 8, 10, 12)

The CD40106BMS is supplied in these 14 lead outline

packages:

VDD

Braze Seal DIP

Frit Seal DIP

H4Q

H1B

H3W

ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION

NETWORK

Ceramic Flatpack

VSS

FIGURE 1. 1 OF 6 SCHMITT TRIGGERS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3354

7-1327

12 3 4 5 6 7...9

中文翻译

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