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CD40103BFMSR PDF预览

CD40103BFMSR

更新时间： 2024-01-15 19:44:00
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件输出元件逻辑集成电路触发器
页数 文件大小 规格书
13页 168K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, CDIP16

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CD40103BFMSR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：FRIT SEALED, DIP-16
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.35
Is Samacsys：N计数方向：DOWN
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：9.585 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：700000 Hz最大I（ol）：0.00036 A
工作模式：SYNCHRONOUS位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 VProp。Delay @ Nom-Sup：1755 ns
传播延迟（tpd）：810 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：5.33 mm
子类别：Counters标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：100k Rad(Si) V触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：0.52 MHz
Base Number Matches：1

CD40103BFMSR 数据手册

 浏览型号CD40103BFMSR的Datasheet PDF文件第2页浏览型号CD40103BFMSR的Datasheet PDF文件第3页浏览型号CD40103BFMSR的Datasheet PDF文件第4页浏览型号CD40103BFMSR的Datasheet PDF文件第5页浏览型号CD40103BFMSR的Datasheet PDF文件第6页浏览型号CD40103BFMSR的Datasheet PDF文件第7页 
CD40102BMS  
CD40103BMS  
CMOS 8-Stage Presettable  
Synchronous Down Counters  
December 1992  
Features  
Description  
• High Voltage Type (20V Rating)  
• CD40102BMS: 2-Decade BCD Type  
• CD40103BMS: 8-Bit Binary Type  
• Synchronous or Asynchronous Preset  
CD40102BMS and CD40103BMS consist of an 8-stage syn-  
chronous down counter with a single output which is active  
when the internal count is zero. The CD40102BMS is config-  
ured as two cascaded 4-bit BCD counters, and the  
CD40103BMS contains a single 8-bit binary counter. Each  
type has control inputs for enabling or disabling the clock, for  
clearing the counter to its maximum count, and for presetting  
the counter either synchronously or asynchronously. All con-  
trol inputs and the CARRY-OUT/ZERO-DETECT output are  
active-low logic.  
• Medium Speed Operation  
- fCL = 3.6MHz (Typ) at 10V  
• Cascadable  
• 100% Tested for Quiescent Current at 20V  
In normal operation, the counter is decremented by one  
count on each positive transition of the CLOCK. Counting is  
inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)  
inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD)  
output goes low when the count reaches zero if the CI/CE  
input is low, and remains low for one full clock period.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
When the SYNCHRONOUS PRESET-ENABLE (SPE) input  
is low, data at the JAM input is clocked into the counter on  
the next positive clock transition regardless of the state of  
the CI/CE input. When the ASYNCHRONOUS PRESET-  
ENABLE (APE) input is low, data at the JAM inputs is asyn-  
chronously forced into the counter regardless of the state of  
the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 repre-  
sent two 4-bit BCD words for the CD40102BMS and a single  
8-bit binary word for the CD40103BMS.  
- 2.5V at VDD = 15V  
• Standardized Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
When the CLEAR (CLR) input is low, the counter is asyn-  
chronously cleared to its maximum count (9910 for the  
CD40102BMS and 25510 for the CD40103BMS) regardless  
of the state of any other input. The precedence relationship  
between control inputs is indicated in the truth table.  
Applications  
• Divide-By- “N” Counters  
• Programmable Times  
• Interrupt Timers  
If all control inputs except CI/CE are high at the time of zero  
count, the counters will jump to the maximum count, giving a  
counting sequence of 100 or 256 clock pulses long.  
• Cycle/Program Counter  
This causes the CO/ZD output to go low to enable the clock  
on each succeeding clock pulse.  
Pinout  
CD40102BMS, CD40130BMS  
The CD40102BMS and CD40103BMS may be cascaded  
using the CI/CE input and the CO/ZD output, in either a syn-  
chronous or ripple mode as shown in Figures 16 and 17.  
TOP VIEW  
CLOCK  
CLEAR  
1
2
3
4
5
6
7
8
16 VDD  
The CD40102MS and CD40103BMS are supplied in these  
16-lead outline packages:  
SYNCHRONOUS  
PRESET ENABLE  
CARRY OUT/  
15  
14  
CARRY IN/  
COUNTER ENABLE  
ZERO DETECT  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
*CD40102B Only  
*H4W †H4X  
J0  
13 J7  
12 J6  
11 J5  
10 J4  
*H1L  
H6W  
†H1F  
J1  
J2  
†CD40130B Only  
J3  
9
ASYNCHRONOUS  
PRESET ENABLE  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3351  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1294  
1234567...13

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