CAV25256
256-Kb SPI Serial CMOS
EEPROM
Description
The CAV25256 is a 256−Kb Serial CMOS EEPROM device
internally organized as 32Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAV25256 device. The device features
software and hardware write protection, including partial as well as
full array protection.
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz (5 V) SPI Compatible
TSSOP−8
Y SUFFIX
CASE 948AL
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
PIN CONFIGURATIONS
• 64−byte Page Write Buffer
1
V
CC
CS
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
SO
HOLD
WP
SCK
V
SS
SI
• Hardware and Software Protection
SOIC (V), TSSOP (Y)
(Top View)
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PIN FUNCTION
Pin Name
CS
Function
Chip Select
• 8−lead SOIC and TSSOP Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SO
Serial Data Output
Write Protect
Ground
WP
V
CC
V
SS
SI
Serial Data Input
Serial Clock
SI
SCK
CS
HOLD
Hold Transmission Input
Power Supply
SO
CAV25256
WP
V
CC
HOLD
SCK
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2013 − Rev. 0
CAV25256/D