CAV25512H
512-Kb SPI Serial CMOS
EEPROM
Description
The CAV25512H is a 512−Kb Serial CMOS EEPROM device
internally organized as 64Kx8 bits. This features a 128−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAV25512H device. The device
features software and hardware write protection, including partial as
well as full array protection.
www.onsemi.com
UDFN−8
HU5 SUFFIX
CASE 517BU
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
PIN CONFIGURATION
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
V
1
CS
CC
HOLD
SCK
SI
SO
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
WP
• 128−byte Page Write Buffer
V
SS
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
UDFN (HU5)
(Top View)
• Hardware and Software Protection
• Block Write Protection
PIN FUNCTION
1
1
− Protect / , / or Entire EEPROM Array
4
2
Pin Name
CS
Function
Chip Select
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
SO
Serial Data Output
Write Protect
Ground
WP
• UDFN 8−lead Package
V
SS
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SI
Serial Data Input
Serial Clock
V
CC
SCK
HOLD
Hold Transmission Input
Power Supply
SI
V
CC
CS
CAV25512H
SO
WP
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
HOLD
SCK
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2016 − Rev. 0
CAV25512H/D