CAV25512
512-Kb SPI Serial CMOS
EEPROM
Description
The CAV25512 is a 512−Kb Serial CMOS EEPROM device
internally organized as 64Kx8 bits. This features a 128−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAV25512 device. The device
features software and hardware write protection, including partial as
well as full array protection.
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
TSSOP−8
Y SUFFIX
CASE 948AL
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 128−byte Page Write Buffer
PIN CONFIGURATION
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
1
CS
SO
WP
V
CC
• Hardware and Software Protection
• Block Write Protection
HOLD
SCK
SI
1
1
− Protect / , / or Entire EEPROM Array
4
2
V
SS
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
SOIC (V), TSSOP (Y)
• SOIC and TSSOP 8−lead Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN FUNCTION
Pin Name
CS
Function
Chip Select
V
CC
SO
Serial Data Output
Write Protect
WP
SI
V
SS
Ground
CS
SI
Serial Data Input
Serial Clock
CAV25512
SO
WP
SCK
HOLD
SCK
HOLD
Hold Transmission Input
Power Supply
V
CC
V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2013 − Rev. 0
CAV25512/D