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CAT28F020-12 PDF预览

CAT28F020-12

更新时间: 2024-10-31 22:40:47
品牌 Logo 应用领域
CATALYST 闪存
页数 文件大小 规格书
14页 104K
描述
2 Megabit CMOS Flash Memory

CAT28F020-12 数据手册

 浏览型号CAT28F020-12的Datasheet PDF文件第2页浏览型号CAT28F020-12的Datasheet PDF文件第3页浏览型号CAT28F020-12的Datasheet PDF文件第4页浏览型号CAT28F020-12的Datasheet PDF文件第5页浏览型号CAT28F020-12的Datasheet PDF文件第6页浏览型号CAT28F020-12的Datasheet PDF文件第7页 
Licensed Intel  
second source  
CAT28F020  
2 Megabit CMOS Flash Memory  
FEATURES  
Commercial, Industrial and Automotive  
Fast Read Access Time: 70/90/120 ns  
Temperature Ranges  
Low Power CMOS Dissipation:  
– Active: 30 mA max (CMOS/TTL levels)  
– Standby: 1 mA max (TTL levels)  
– Standby: 100 µA max (CMOS levels)  
Stop Timer for Program/Erase  
On-Chip Address and Data Latches  
JEDEC Standard Pinouts:  
– 32-pin DIP  
High Speed Programming:  
– 10 µs per byte  
– 32-pin PLCC  
– 32-pin TSOP (8 x 20)  
– 4 Seconds Typical Chip Program  
100,000 Program/Erase Cycles  
10 Year Data Retention  
Electronic Signature  
0.5 Seconds Typical Chip-Erase  
12.0V ± 5% Programming and Erase Voltage  
DESCRIPTION  
using a two write cycle scheme. Address and Data are  
latched to free the I/O bus and address bus during the  
write operation.  
TheCAT28F020isahighspeed256Kx8-bitelectrically  
erasable and reprogrammable Flash memory ideally  
suited for applications requiring in-system or after-sale  
code updates. Electrical erasure of the full memory  
contents is achieved typically within 0.5 second.  
The CAT28F020 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles and has a data  
retention of 10 years. The device is available in JEDEC  
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin  
TSOP packages.  
It is pin and Read timing compatible with standard  
EPROM and E2PROM devices. Programming and  
Erase are performed through an operation and verify  
algorithm. The instructions are input via the I/O bus,  
BLOCK DIAGRAM  
I/O –I/O  
0
7
I/O BUFFERS  
ERASE VOLTAGE  
SWITCH  
WE  
DATA  
LATCH  
SENSE  
AMP  
COMMAND  
REGISTER  
PROGRAM VOLTAGE  
SWITCH  
CE, OE LOGIC  
CE  
OE  
Y-GATING  
Y-DECODER  
2,097,152 BIT  
MEMORY  
ARRAY  
A –A  
17  
0
X-DECODER  
VOLTAGE VERIFY  
SWITCH  
5115 FHD F02  
© 1998 by Catalyst Semiconductor, Inc.  
Doc. No. 25037-00 2/98 F-1  
Characteristics subject to change without notice  
1

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