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BUK9614-55 PDF预览

BUK9614-55

更新时间: 2024-11-30 22:50:23
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
8页 58K
描述
TrenchMOS transistor Logic level FET

BUK9614-55 技术参数

生命周期:Obsolete零件包装代码:SOT
包装说明:SMALL OUTLINE, R-PSSO-G2针数:3
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.75其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED
雪崩能效等级(Eas):200 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:55 V
最大漏极电流 (ID):68 A最大漏源导通电阻:0.014 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G2
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):240 A
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:SINGLE
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

BUK9614-55 数据手册

 浏览型号BUK9614-55的Datasheet PDF文件第2页浏览型号BUK9614-55的Datasheet PDF文件第3页浏览型号BUK9614-55的Datasheet PDF文件第4页浏览型号BUK9614-55的Datasheet PDF文件第5页浏览型号BUK9614-55的Datasheet PDF文件第6页浏览型号BUK9614-55的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
BUK9614-55  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode logic  
level field-effect power transistor in a  
plastic envelope suitable for surface  
mounting. Using ’trench’ technology  
the device features very low on-state  
resistance and has integral zener  
diodes giving ESD protection up to  
2kV. It is intended for use in  
automotive and general purpose  
switching applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Ptot  
Tj  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Junction temperature  
Drain-source on-state  
55  
68  
142  
175  
14  
V
A
W
˚C  
m  
RDS(ON)  
resistance  
VGS = 5 V  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
mb  
gate  
2
drain  
g
3
source  
2
mb drain  
s
1
3
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
ID  
IDM  
Drain-source voltage  
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
-
-
-
-
-
-
-
-
55  
55  
10  
68  
48  
240  
142  
175  
V
V
V
A
A
A
W
˚C  
RGS = 20 kΩ  
-
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
-
Drain current (DC)  
Drain current (pulse peak value)  
Total power dissipation  
Storage & operating temperature  
Ptot  
Tstg, Tj  
- 55  
ESD LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VC  
Electrostatic discharge capacitor  
voltage  
Human body model  
(100 pF, 1.5 k)  
-
2
kV  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-mb  
Thermal resistance junction to  
mounting base  
-
-
1.05  
K/W  
Rth j-a  
Thermal resistance junction to  
ambient  
Minimum footprint, FR4  
board  
50  
-
K/W  
April 1998  
1
Rev 1.000  

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