Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BS62LV2007
BSI
DESCRIPTION
FEATURES
The BS62LV2007 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
The BS62LV2007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2007 is available in the JEDEC standard 36 pin
Mini BGA 6x8 mm.
-70
-10
70ns(Max.) at Vcc = 3.0V
100ns(Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG
(ICCSB1, Max)
(ICC, Max)
Vcc=
TEMPERATURE
RANGE
TYPE
Vcc=
Vcc=
Vcc=
3.0V
Vcc=
3.0V
3.0V
5.0V
5.0V
BS62LV2007HC
BS62LV2007HI
0 O C to +70 O C
70/100
70/100
6 uA
0.7 uA
1.5 uA
35 mA
20 mA
25 mA
BGA-36-
0608
2.4V ~5.5V
-40 O C to +85O C
25 uA
40 mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
A13
A17
A15
Address
Memory Array
1024 x 2048
A16
20
1024
Row
A14
A12
A7
Input
Decoder
Buffer
A6
A5
A4
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
8
8
Data
256
Output
Buffer
Column Decoder
16
CE1
CE2
WE
Control
Address Input Buffer
OE
Vdd
Gnd
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.0
April 2002
R0201-BS62LV2007
1