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BQ4832Y PDF预览

BQ4832Y

更新时间: 2024-09-14 22:39:39
品牌 Logo 应用领域
德州仪器 - TI 静态存储器
页数 文件大小 规格书
18页 679K
描述
RTC Module With 32Kx8 NVSRAM

BQ4832Y 数据手册

 浏览型号BQ4832Y的Datasheet PDF文件第2页浏览型号BQ4832Y的Datasheet PDF文件第3页浏览型号BQ4832Y的Datasheet PDF文件第4页浏览型号BQ4832Y的Datasheet PDF文件第5页浏览型号BQ4832Y的Datasheet PDF文件第6页浏览型号BQ4832Y的Datasheet PDF文件第7页 
bq4832Y  
RTC Module With 32Kx8 NVSRAM  
Features  
General Description  
Registers for the rea l-time clock,  
alarm and other special functions  
Integrated SRAM, real-time  
clock, CPU supervisor, crystal,  
power-fail circuit, and battery  
The bq4832Y RTC Module is a non-  
volatile 262,144-bit SRAM organ-  
ized as 32,768 words by 8 bits with  
an integral real-time clock and CPU  
supervisor. The CPU supervisor pro-  
vides a pr ogr a m m a ble wa t ch dog  
timer and a microprocessor reset.  
O t h e r fe a t u r e s in clu d e a la r m ,  
power-fail, and periodic interrupts,  
and a battery-low warning.  
a r e loca t ed in r egist er s 7F F 0h –  
7FFFh of the memory array.  
The clock and alarm registers are  
du a l-por t r ea d/wr it e SRAM loca-  
tions that are updated once per sec-  
ond by a clock control circuit from  
the internal clock counters. The  
dual-port registers allow clock up-  
dates to occur without interrupting  
n or m a l a ccess t o t h e r est of t h e  
SRAM array.  
Real-Time Clock counts hun-  
dredths of seconds through years  
in BCD format  
RAM-like clock access  
Compatible with industry-  
standard 32K x 8 SRAMs  
Th e device com bin es a n in t er n a l  
lithium battery, quartz crystal, clock  
a n d p ower -fa il ch ip, a n d a fu ll  
CMOS SRAM in a pla st ic 32-pin  
DIP module. The RTC Module di-  
rectly replaces industry-standard  
SRAMs a n d a lso fit s in t o m a n y  
E P R O M a n d E E P R O M s ock e t s  
without any requirement for special  
write timing or limitations on the  
number of write cycles.  
Unlimited write cycles  
The bq4832Y also contains a power-  
fail-detect circuit. The circuit dese-  
lects the device whenever VCC falls  
below tolerance, providing a high de-  
gree of data security. The battery is  
electrically isolated when shipped  
from the factory to provide maxi-  
mum battery capacity. The battery  
remains disconnected until the first  
10-year minimum data retention  
and clock operation in the ab-  
sence of power  
Automatic power-fail chip dese-  
lect and write-protection  
Watchdog timer, power-on reset,  
alarm/periodic interrupt, power-  
fail and battery-low warning  
application of VCC  
.
Software clock calibration for  
greater than ±1 minute per  
month accuracy  
Pin Names  
Pin Connections  
A0–A14  
Address input  
RST  
NC  
32  
1
V
CC  
NC  
INT  
CE  
Chip enable  
31  
30  
2
3
A
14  
RST  
WE  
Microprocessor reset  
Write enable  
4
WE  
A
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
12  
5
A
A
A
A
A
A
A
13  
7
6
5
4
3
2
6
A
8
A
9
A
11  
OE  
7
OE  
Output enable  
8
9
DQ0–DQ7 Data in/data out  
10  
11  
12  
13  
14  
15  
16  
A
10  
CE  
DQ  
DQ  
DQ  
DQ  
DQ  
A
1
0
0
1
2
INT  
VCC  
VSS  
Programmable interrupt  
A
DQ  
DQ  
DQ  
V
7
6
5
4
3
+5 volts  
Ground  
SS  
32-Pin DIP Module  
PN483201.eps  
Sept. 1996 C  
1

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