VCE6467T, AVCE6467T
www.ti.com
SPRS690–MARCH 2011
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the VCE6467T SoC. The table shows significant features of the device,
including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+
DSP, and the package type with pin count.
Table 2-1. Characteristics of the VCE6467T Processor
HARDWARE FEATURES
VCE6467T
DDR2 Memory Controller
DDR2 (Up to 400-MHz, 16/32-bit bus width)
Asynchronous (8/16-bit bus width) RAM, Flash
(NOR, NAND)
Asynchronous EMIF (EMIFA)
EDMA
64 independent channels
8 QDMA channels
2 64-Bit General Purpose (each configurable as 2
separate 32-bit timers)
Timers
UART
1 64-Bit Watchdog
3 (with SIR, MIR, CIR support and RTS/CTS flow
control)
(UART0 Supports Modem Interface)
SPI
I2C
1 (supports 2 slave devices)
1 (Master/Slave)
2 (one transmit/receive with 4 serializers,
one DIT transmit only with 1 serializer for S/PDIF
output)
Multichannel Audio Serial Port (McASP)
10/100/1000 Ethernet MAC with Management Data
Input/Output (MDIO)
1 (with MII/GMII Interface)
Peripherals
VLYNQ
1
Up to 33 pins
Not all peripherals pins are
available at the same time
(for more detail, see the
Device Configurations
section).
General-Purpose Input/Output Port (GPIO)
PWM
ATA
PCI
2 outputs
1 (ATA/ATAPI-6)
1 (32-bit, 66 MHz)
1 (16-/32-bit multiplexed address/data)
HPI
1 [horizontal and vertical downscaling,
chroma conversion (4:2:2↔4:2:0)]
VDCE
Clock Recovery Generator (CRGEN)
Power Sleep Controller (PSC)
1
1 (peripheral/module clock gating)
2 8-bit BT.656 capture channels or
1 16-bit Y/C capture channel or
108-MHz Configurable Video Port Interface (VPIF)
1 8-/10-/12-bit raw video capture channel and
2 8-bit BT.656 display channels or
1 16-bit Y/C display channel
MPEG transport stream interface
1 with 8-bit parallel or serial input and output
Transport Stream Interface (TSIF)
1 with serial-only input and output
Each with corresponding clock recovery generator
(CRGEN) for external VCXO control.
High- and Full-Speed Device
High-, Full-, and Low-Speed Host
(1)
USB 2.0
(1) USB2.0 is not supported on -1G parts that are dated prior to May 1, 2010. See the TMS320DM6467T Silicon Errata (Literature Number:
SPRZ307) for more details on how to decode the date from package markings.
Copyright © 2011, Texas Instruments Incorporated
Device Overview
7
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Product Folder Link(s): VCE6467T AVCE6467T