VCE6467T, AVCE6467T
SPRS690–MARCH 2011
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Table 2-1. Characteristics of the VCE6467T Processor (continued)
HARDWARE FEATURES
VCE6467T
Size (Bytes)
248KB RAM, 8KB ROM
DSP
•
•
•
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
On-Chip Memory
Organization
ARM
•
•
•
•
16KB I-cache
8KB D-cache
32KB RAM
8KB ROM
CPU ID + CPU Rev ID
Control Status Register (CSR.[31:16])
0x1000
0x0000
C64x+ Megamodule
Revision
Revision ID Register (MM_REVID[15:0])
(address location: 0x0181 2000)
JTAGID Register
(address location: 0x01C4 0028)
See Section 6.29.1, JTAG ID (JTAGID) Register
JTAG BSDL_ID
CPU Frequency
Description(s)
DSP 1 GHz (-1G)
ARM926 500 MHz(-1G)
DSP 1.0 ns (-1G)
ARM926 2.0 ns (-1G)
1.3 V (-1G)
MHz
ns
Cycle Time
Voltage
Core (V)
I/O (V)
1.8 V, 3.3 V (-1G)
DEV_CLKIN frequency multiplier (PLLC1)
(Between 27 – 35-MHz range)
x1 (Bypass), x14 to x32 (-1G)
x1 (Bypass), x14 to x32 (-1G)
PLL Options
DEV_CLKIN frequency multiplier (PLLC2)
(Between 27 – 35-MHz range)
AUX_CLKIN frequency
19 x 19 mm
μm
24/48-MHz reference
529-Pin BGA (ZUT)
0.09 μm
BGA Package
Process Technology
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(2)
PD
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8
Device Overview
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