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AT17C010-10PC PDF预览

AT17C010-10PC

更新时间: 2024-11-27 20:12:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
13页 163K
描述
Configuration Memory, 1MX1, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8

AT17C010-10PC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP8,.3
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.88最大时钟频率 (fCLK):15 MHz
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.398 mm内存密度:1048576 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
功能数量:1端子数量:8
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX1
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:4.318 mm
子类别:EEPROMs最大压摆率:0.01 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
写保护:HARDWAREBase Number Matches:1

AT17C010-10PC 数据手册

 浏览型号AT17C010-10PC的Datasheet PDF文件第2页浏览型号AT17C010-10PC的Datasheet PDF文件第3页浏览型号AT17C010-10PC的Datasheet PDF文件第4页浏览型号AT17C010-10PC的Datasheet PDF文件第5页浏览型号AT17C010-10PC的Datasheet PDF文件第6页浏览型号AT17C010-10PC的Datasheet PDF文件第7页 
Features  
EE Programmable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store  
Configuration Programs for Field Programmable Gate Arrays (FPGAs)  
In-System Programmable via 2-wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX® Devices, Lucent ORCA®  
FPGAs, Xilinx XC3000, XC4000, XC5200, SPARTAN® and Virtex® FPGAs  
Cascadable Read Back to Support Additional Configurations or Future  
Higher-density Arrays  
Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
FPGA  
Available in PLCC Package (Pin-compatible Across Product Family)  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Available in 3.3V 10% LV and 5V 5% C Versions  
System-friendly READY Pin  
Configuration  
EEPROM  
Memory  
Low-power Standby Mode  
Description  
512K and 1M  
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA  
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-  
figuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged  
in the popular 20-pin PLCC. The AT17 Series family uses a simple serial-access pro-  
cedure to configure one or more FPGA devices. The AT17 Series organization  
supplies enough memory to configure one or multiple smaller FPGAs. The user can  
select the polarity of the reset function by programming four EEPROM bytes. These  
devices also support a write protection mode and a system-friendly READY pin, which  
signifies a “good” power level to the FPGA and can be used to ensure reliable system  
power-up.  
AT17C512  
AT17LV512  
AT17C010  
AT17LV010  
The AT17 Configurator Series can be programmed with industry-standard  
programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
Pin Configurations  
20 PLCC  
8 LAP  
DATA  
CLK  
1
2
3
4
8
7
6
5
VCC  
CLK  
WP1  
4
5
6
7
8
18 NC  
17 SER_EN  
16 NC  
SER_EN  
CEO (A2)  
GND  
RESET/OE  
WP2  
15 READY  
14 CEO (A2)  
RESET/OE  
CE  
CE  
8 PDIP  
DATA  
1
2
3
4
8
7
6
5
VCC  
CLK  
RESET/OE  
CE  
SER_EN  
CEO (A2)  
GND  
Rev. 0944D–06/01  

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