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AT17C128-10NC PDF预览

AT17C128-10NC

更新时间: 2024-10-26 20:26:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟ATM异步传输模式光电二极管内存集成电路
页数 文件大小 规格书
15页 177K
描述
Configuration Memory, 128KX1, 50ns, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8

AT17C128-10NC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.91Is Samacsys:N
最长访问时间:50 ns最大时钟频率 (fCLK):12.5 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.89 mm内存密度:131072 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX1
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.73 mm
最大待机电流:0.000075 A子类别:EEPROMs
最大压摆率:0.01 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

AT17C128-10NC 数据手册

 浏览型号AT17C128-10NC的Datasheet PDF文件第2页浏览型号AT17C128-10NC的Datasheet PDF文件第3页浏览型号AT17C128-10NC的Datasheet PDF文件第4页浏览型号AT17C128-10NC的Datasheet PDF文件第5页浏览型号AT17C128-10NC的Datasheet PDF文件第6页浏览型号AT17C128-10NC的Datasheet PDF文件第7页 
Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories  
Designed to Store Configuration Programs for Field Programmable Gate  
Arrays (FPGAs)  
In-System Programmable (ISP) via 2-wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX®, APEXDevices, Lucent  
ORCA® FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan®, VirtexFPGAs,  
Motorola MPA1000 FPGAs  
Cascadable Read-back to Support Additional Configurations (128K and 256K Only)  
Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available in the Space-efficient Plastic DIP or SOIC Packages; PLCC Package is  
Pin-compatible across Product Family  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Available in 3.3V 10% LV and 5V 5% C Versions  
Low-power Standby Mode  
FPGA  
Configuration  
EEPROM  
Memory  
Description  
64K, 128K and 256K  
The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 series) FPGA  
configuration EEPROMs (configurators) provide an easy-to-use, cost-effective config-  
uration memory for field programmable gate arrays. The low-density AT17 series is  
packaged in the 8-lead PDIP, 8-lead SOIC and the popular 20-lead PLCC and SOIC.  
The AT17 series family uses a simple serial-access procedure to configure one or  
more FPGA devices. The AT17 series organization supplies enough memory to con-  
figure one or multiple smaller FPGAs. Using a feature of the AT17 series, the user can  
select the polarity of the reset function by programming a special EEPROM byte.  
These devices also support a write-protection mechanism within its programming  
mode.  
AT17C65  
AT17LV65  
AT17C128  
AT17LV128  
AT17C256  
AT17LV256  
The AT17 Series Configurators can be programmed with industry-standard program-  
mers, or Atmel’s ATDH2200E Programming Kit.  
Pin Configurations  
20-lead PLCC  
20-lead SOIC  
NC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
NC  
DATA  
NC  
NC  
CLK  
4
5
6
7
8
18 NC  
CLK  
SER_EN  
NC  
NC  
17 SER_EN  
16 NC  
NC  
(WP) RESET/OE  
(WP) RESET/OE  
NC  
1
NC  
CE  
15 NC (READY)  
14 CEO (A2)  
NC  
CE  
CEO (A2)  
NC  
NC  
NC  
GND  
NC  
8-lead PDIP  
8-lead SOIC  
DATA  
1
2
3
4
8
7
6
5
VCC  
DATA  
1
2
3
4
8
VCC  
CLK  
(WP) RESET/OE  
CE  
SER_EN  
CEO (A2)  
GND  
CLK  
(WP) RESET/OE  
CE  
7
6
5
SER_EN  
CEO (A2)  
GND  
Rev. 1636C–04/01  
Note:  
1. READY pin is available on new parts only. See page 12.  

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