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ASM3P622S00BG-08-SR PDF预览

ASM3P622S00BG-08-SR

更新时间: 2024-09-13 06:38:11
品牌 Logo 应用领域
PULSECORE 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
15页 545K
描述
Low Frequency Timing-Safe™ Peak EMI reduction IC

ASM3P622S00BG-08-SR 技术参数

生命周期:Transferred包装说明:0.150 INCH, LEAD FREE, SOIC-8
Reach Compliance Code:unknown风险等级:5.76
JESD-30 代码:R-PDSO-G8长度:4.9 mm
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:20 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
主时钟/晶体标称频率:20 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.91 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ASM3P622S00BG-08-SR 数据手册

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May 2008  
rev 0.5  
ASM3P622S00B/E  
Low Frequency Timing-Safe™ Peak EMI reduction IC  
one reference input and drives out eight low-skew Timing-  
Safe™clocks.  
General Features  
Low Frequency Clock distribution with Timing-  
ASM3P622S00B/E has an SS% that selects 2 different  
Deviation and associated Input-Output Skew (TSKEW). Refer  
Spread Spectrum Control and Input-Output Skew table  
for details.  
Safe™ Peak EMI Reduction  
Input frequency range: 4MHz - 20MHz  
2 different Spread Selection option  
Spread Spectrum can be turned ON/OFF  
External Input-Output Delay Control option  
Supply Voltage: 3.3V±0.3V  
ASM3P622S00E has a CLKOUT for adjusting the Input-  
Output clock delay, depending upon the value of capacitor  
connected at this pin to GND.  
Commercial and Industrial temperature range  
Packaging Information:  
ASM3P622S00B: 8 pin SOIC, and TSSOP  
ASM3P622S00E:16 pin SOIC, and TSSOP  
The First True Drop-in Solution  
ASM3P622S00B/E operates from a 3.3V supply and is  
available in two different packages, as shown in the  
ordering information table, over commercial and Industrial  
temperature range.  
Functional Description  
Application  
ASM3P622S00B/E is a versatile, 3.3V Zero-delay buffer  
designed to distribute low frequency Timing-Safe™ clocks  
with Peak EMI reduction. ASM3P622S00B is an eight-pin  
version, accepts one reference input and drives out one  
low-skew Timing-Safe™ clock. ASM3P622S00E accepts  
ASM3P622S00B/E is targeted for use in Displays and  
memory interface systems.  
General Block Diagram  
VDD  
DLY_CTRL  
SS%  
CLKIN  
PLL  
CLKOUT(s)*  
(Timing-Safe™)  
*For  
ASM3P622S00E -  
8 CLKOUTS  
SSON  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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