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ASM3P622S00JF-08-SR

更新时间： 2024-11-27 06:38:11

品牌	Logo	应用领域
PULSECORE		/
页数	文件大小	规格书
16页	712K
描述
Low Frequency Timing-Safe™ Peak EMI reduction IC

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ASM3P622S00JF-08-SR 技术参数

生命周期：	Obsolete	包装说明：	0.150 INCH, LEAD FREE, SOIC-8
Reach Compliance Code：	unknown	风险等级：	5.76
JESD-30 代码：	R-PDSO-G8	长度：	4.9 mm
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	20 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
主时钟/晶体标称频率：	20 MHz	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.91 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

ASM3P622S00JF-08-SR 数据手册

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May 2007

rev 0.4

ASM3P622S00A/B/J/E/K

Low Frequency Timing-Safe™ Peak EMI reduction IC

General Features

one reference input and drives out one low-skew clock.

•

Low Frequency Clock distribution with Timing-

All parts have on-chip PLLs that lock to an input clock on

the XIN/CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Safe™ Peak EMI Reduction

•

Input frequency range: 4MHz - 20MHz

Zero input - output propagation delay

Low-skew outputs

Multiple ASM3P622S00E/K devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

• Output-output skew less than 250pS

• Device-device skew less than 700pS

Less than 200pS cycle-to-cycle jitter

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P622S00E/K), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P622S00A/B/J)

3.3V Operation

Industrial temperature range

Advanced CMOS technology

The First True Drop-in Solution

•

All outputs have less than 200pS of Cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output-to-output skew is

guaranteed to be less than 250pS.

•

Refer “Spread Spectrum Control and Input-Output Skew

Functional Description

Table”

for deviations and Input-Output Skew for

ASM3P622S00A/B/J and ASM3P622S00E/K devices

ASM3P622S00A/B/J/E/K is a versatile, 3.3V Zero-delay

buffer designed to distribute low frequency Timing-Safe™

clocks with Peak EMI reduction. ASM3P622S00E/K

accepts one reference input and drives out eight low-skew

The ASM3P622S00A/B/J and ASM3P622S00E/K are

available in two different packages, as shown in the

ordering information table.

clocks. It is available in

16pin Package. The

ASM3P622S00A/B/J is the eight-pin version and accepts

V_DD

SSON

SS%

Block Diagram

PLL

Modulation

XIN/CLKIN

XOUT

Reference

Divider

Crystal

Oscillator

Feedforward

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

CLKOUT

GND

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...16

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与ASM3P622S00JF-08-SR相关器件

型号	品牌	获取价格	描述	数据表
ASM3P622S00JF-08-ST	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JF-08-TR	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JF-08-TT	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JG-08-SR	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JG-08-ST	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JG-08-TR	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00JG-08-TT	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00K	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00KF-16-SR	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction
ASM3P622S00KF-16-ST	PULSECORE	获取价格	Low Frequency Timing-Safe™ Peak EMI reduction

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