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ASM3P622S00KG-16-SR PDF预览

ASM3P622S00KG-16-SR

更新时间: 2024-11-05 06:38:11
品牌 Logo 应用领域
PULSECORE 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
16页 712K
描述
Low Frequency Timing-Safe™ Peak EMI reduction IC

ASM3P622S00KG-16-SR 技术参数

生命周期:Obsolete包装说明:0.150 INCH, GREEN, SOIC-16
Reach Compliance Code:unknown风险等级:5.76
Is Samacsys:NJESD-30 代码:R-PDSO-G16
长度:9.905 mm端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:20 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE主时钟/晶体标称频率:20 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ASM3P622S00KG-16-SR 数据手册

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May 2007  
rev 0.4  
ASM3P622S00A/B/J/E/K  
Low Frequency Timing-Safe™ Peak EMI reduction IC  
General Features  
one reference input and drives out one low-skew clock.  
Low Frequency Clock distribution with Timing-  
All parts have on-chip PLLs that lock to an input clock on  
the XIN/CLKIN pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad, internal to the device.  
Safe™ Peak EMI Reduction  
Input frequency range: 4MHz - 20MHz  
Zero input - output propagation delay  
Low-skew outputs  
Multiple ASM3P622S00E/K devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
Output-output skew less than 250pS  
Device-device skew less than 700pS  
Less than 200pS cycle-to-cycle jitter  
Available in 16pin, 150mil SOIC, 4.4mm TSSOP  
(ASM3P622S00E/K), and in 8pin, 150 mil SOIC,  
4.4mm TSSOP Packages (ASM3P622S00A/B/J)  
3.3V Operation  
Industrial temperature range  
Advanced CMOS technology  
The First True Drop-in Solution  
All outputs have less than 200pS of Cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than ±350pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
Refer Spread Spectrum Control and Input-Output Skew  
Functional Description  
Table”  
for deviations and Input-Output Skew for  
ASM3P622S00A/B/J and ASM3P622S00E/K devices  
ASM3P622S00A/B/J/E/K is a versatile, 3.3V Zero-delay  
buffer designed to distribute low frequency Timing-Safe™  
clocks with Peak EMI reduction. ASM3P622S00E/K  
accepts one reference input and drives out eight low-skew  
The ASM3P622S00A/B/J and ASM3P622S00E/K are  
available in two different packages, as shown in the  
ordering information table.  
clocks. It is available in  
a
16pin Package. The  
ASM3P622S00A/B/J is the eight-pin version and accepts  
VDD  
SSON  
SS%  
Block Diagram  
PLL  
Modulation  
XIN/CLKIN  
XOUT  
Reference  
Divider  
Crystal  
Oscillator  
Feedforward  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
CLKOUT  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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