Datasheet > ASM3P623S00AF-08-TT

ASM3P623S00AF-08-TT

更新时间： 2024-11-05 20:13:35

品牌	Logo	应用领域
PULSECORE		光电二极管
页数	文件大小	规格书
16页	297K
描述
PLL Based Clock Driver, 3P Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 4.40 MM, ROHS COMPLIANT, TSSOP-8

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ASM3P623S00AF-08-TT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSSOP,	Reach Compliance Code：	unknown
风险等级：	5.59	系列：	3P
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G8
长度：	4.4 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	8	实输出次数：	1
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	传播延迟（tpd）：	0.35 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.1 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
Base Number Matches：	1

ASM3P623S00AF-08-TT 数据手册

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July 2005

rev 1.0

ASM3P623S00A/B/C/D/E/F

Zero Cycle Slip Peak EMI reduction IC

General Features

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Input frequency range: 20MHz - 50MHz.

Zero input - output propagation delay.

Low-skew outputs.

Multiple ASM3P623S00D/E/F devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

Output-output skew less than 250pS.

Device-device skew less than 700pS.

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium^®based systems.

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P623S00A/B/C).

3.3V operation

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 250pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Advanced 0.35µ CMOS technology.

The First True Drop-in Solution.

Please refer “Differential Cycle Slips and Spread Spectrum

Control Table” for deviations and differential Cycle Slips

for ASM3P623S00A/B/C and the ASM3P623S00D/E/F

devices

Functional Description

ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It accepts one

reference input and drives out eight low-skew clocks. It is

available in a 16pin package. The ASM3P623S00A/B/C is

the eight-pin version of the ASM3P623S00. It accepts one

reference input and drives out one low-skew clock.

The ASM3P623S00A/B/C and the ASM3P623S00D/E/F

are available in two different configurations, as shown in

the ordering information table.

Block Diagram

V_DD

SS%

SSON

PLL

Modulation

Reference

Divider

CLKIN

Feedforward

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

CLKOUT

V_SS

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...16

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与ASM3P623S00AF-08-TT相关器件

型号	品牌	获取价格	描述	数据表
ASM3P623S00AG-08-SR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-ST	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-TR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-TT	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00B	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3P623S00B_1	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3P623S00BF-08-SR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00BF-08-SR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3P623S00BF-08-ST	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00BF-08-ST	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC

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