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ASM3P623S00BF-08-TT PDF预览

ASM3P623S00BF-08-TT

更新时间: 2024-11-06 06:38:11
品牌 Logo 应用领域
PULSECORE 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
18页 633K
描述
Timing-Safe™ Peak EMI reduction IC

ASM3P623S00BF-08-TT 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP,Reach Compliance Code:unknown
风险等级:5.59Is Samacsys:N
系列:3P输入调节:STANDARD
JESD-30 代码:R-PDSO-G8长度:4.4 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):0.35 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm最小 fmax:50 MHz
Base Number Matches:1

ASM3P623S00BF-08-TT 数据手册

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May 2007  
rev 0.4  
ASM3P623S00B/C/J/E/F/K  
Timing-Safe™ Peak EMI reduction IC  
General Features  
ASM3P623S00B/C/J is the eight-pin version and accepts  
one reference input and drives out one low-skew clock.  
Clock distribution with Timing-Safe™ Peak EMI  
Reduction  
All parts have on-chip PLLs that lock to an input clock on  
the CLKIN pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad, internal to the device.  
Input frequency range: 20MHz - 50MHz  
Zero input - output propagation delay  
Low-skew outputs  
Output-output skew less than 250pS  
Device-device skew less than 700pS  
Multiple ASM3P623S00E/F/K devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
Less than 200pS cycle-to-cycle jitter  
Available in 16pin, 150mil SOIC, 4.4mm TSSOP  
(ASM3P623S00/E/F/K), and in 8pin, 150 mil  
SOIC, 4.4mm TSSOP Packages  
(ASM3P623S00B/C/J)  
3.3V operation  
Industrial temperature range  
Advanced CMOS technology  
The First True Drop-in Solution  
All outputs have less than 200pS of cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than 250pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
Refer Spread Spectrum Control and Input-Output Skew  
Functional Description  
Table”  
for deviations and Input-Output Skew for  
ASM3P623S00B/C/J and the ASM3P623S00E/F/K devices  
ASM3P623S00B/C/J/E/F/K is a versatile, 3.3V zero-delay  
buffer designed to distribute high-speed Timing-Safe™  
clocks with Peak EMI reduction. ASM3P623S00E/F/K  
accepts one reference input and drives out eight low-skew  
The ASM3P623S00B/C/J and the ASM3P623S00E/F/K are  
available in two different packages, as shown in the  
ordering information table.  
clocks. It is available in  
a
16pin package. The  
Block Diagram  
VDD  
SSON  
SS%  
PLL  
Modulation  
XIN/CLKIN  
Crystal  
Reference  
Divider  
XOUT  
Oscillator  
Feedforward  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
CLKOUT  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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