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ASM3P623S00BF-08-TT PDF预览

ASM3P623S00BF-08-TT

更新时间: 2024-11-05 22:07:03
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ALSC 时钟驱动器逻辑集成电路光电二极管
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16页 297K
描述
Zero Cycle Slip Peak EMI reduction IC

ASM3P623S00BF-08-TT 数据手册

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July 2005  
rev 1.0  
ASM3P623S00A/B/C/D/E/F  
Zero Cycle Slip Peak EMI reduction IC  
General Features  
All parts have on-chip PLLs that lock to an input clock on  
the CLKIN pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad, internal to the device.  
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Input frequency range: 20MHz - 50MHz.  
Zero input - output propagation delay.  
Low-skew outputs.  
Multiple ASM3P623S00D/E/F devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
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Output-output skew less than 250pS.  
Device-device skew less than 700pS.  
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Less than 200pS cycle-to-cycle jitter is compatible  
with Pentium® based systems.  
Available in 16pin, 150mil SOIC, 4.4mm TSSOP  
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,  
4.4mm TSSOP Packages (ASM3P623S00A/B/C).  
3.3V operation  
All outputs have less than 200pS of cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than 250pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
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Advanced 0.35µ CMOS technology.  
The First True Drop-in Solution.  
Please refer Differential Cycle Slips and Spread Spectrum  
Control Table” for deviations and differential Cycle Slips  
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F  
devices  
Functional Description  
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer  
designed to distribute high-speed clocks. It accepts one  
reference input and drives out eight low-skew clocks. It is  
available in a 16pin package. The ASM3P623S00A/B/C is  
the eight-pin version of the ASM3P623S00. It accepts one  
reference input and drives out one low-skew clock.  
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F  
are available in two different configurations, as shown in  
the ordering information table.  
Block Diagram  
VDD  
SS%  
SSON  
PLL  
Modulation  
Reference  
Divider  
CLKIN  
Feedforward  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
CLKOUT  
VSS  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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