Datasheet > 逻辑 > 时钟驱动器> ASM3P623S00AF-08-SR

ASM3P623S00AF-08-SR

更新时间： 2024-11-04 22:06:59

品牌	Logo	应用领域
ALSC		时钟驱动器逻辑集成电路光电二极管 ISM频段
页数	文件大小	规格书
16页	297K
描述
Zero Cycle Slip Peak EMI reduction IC

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ASM3P623S00AF-08-SR 数据手册

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第2页

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第3页

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第4页

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第5页

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第6页

浏览型号ASM3P623S00AF-08-SR的Datasheet PDF文件第7页

July 2005

rev 1.0

ASM3P623S00A/B/C/D/E/F

Zero Cycle Slip Peak EMI reduction IC

General Features

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Input frequency range: 20MHz - 50MHz.

Zero input - output propagation delay.

Low-skew outputs.

Multiple ASM3P623S00D/E/F devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

Output-output skew less than 250pS.

Device-device skew less than 700pS.

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium^®based systems.

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P623S00A/B/C).

3.3V operation

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 250pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Advanced 0.35µ CMOS technology.

The First True Drop-in Solution.

Please refer “Differential Cycle Slips and Spread Spectrum

Control Table” for deviations and differential Cycle Slips

for ASM3P623S00A/B/C and the ASM3P623S00D/E/F

devices

Functional Description

ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It accepts one

reference input and drives out eight low-skew clocks. It is

available in a 16pin package. The ASM3P623S00A/B/C is

the eight-pin version of the ASM3P623S00. It accepts one

reference input and drives out one low-skew clock.

The ASM3P623S00A/B/C and the ASM3P623S00D/E/F

are available in two different configurations, as shown in

the ordering information table.

Block Diagram

V_DD

SS%

SSON

PLL

Modulation

Reference

Divider

CLKIN

Feedforward

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

CLKOUT

V_SS

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...16

中文翻译

下载PDF

与ASM3P623S00AF-08-SR相关器件

型号	品牌	获取价格	描述	数据表
ASM3P623S00AF-08-ST	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AF-08-TR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AF-08-TT	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AF-08-TT	PULSECORE	获取价格	PLL Based Clock Driver, 3P Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 4.
ASM3P623S00AG-08-SR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-ST	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-TR	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00AG-08-TT	ALSC	获取价格	Zero Cycle Slip Peak EMI reduction IC
ASM3P623S00B	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3P623S00B_1	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC

与ASM3P623S00AF-08-SR相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM3P623S00AF-08-SR

ASM3P623S00AF-08-SR 数据手册

与ASM3P623S00AF-08-SR相关器件

与ASM3P623S00AF-08-SR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM3P623S00AF-08-SR

ASM3P623S00AF-08-SR 数据手册

与ASM3P623S00AF-08-SR相关器件

与ASM3P623S00AF-08-SR相关文章

您还可以找

您在本页遇到什么问题？