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ASM2I3805EG-20-AT PDF预览

ASM2I3805EG-20-AT

更新时间: 2024-11-24 20:12:11
品牌 Logo 应用领域
PULSECORE 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 191K
描述
Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, GREEN, SSOP-20

ASM2I3805EG-20-AT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:0.150 INCH, GREEN, SSOP-20Reach Compliance Code:unknown
风险等级:5.64系列:3805
输入调节:STANDARDJESD-30 代码:R-PDSO-G20
JESD-609代码:e3/e6长度:8.649 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:2
反相输出次数:端子数量:20
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):2.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.753 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN/TIN BISMUTH
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

ASM2I3805EG-20-AT 数据手册

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January 2006  
rev 0.2  
ASM2P3805E  
3.3V CMOS Dual 1-To-5 Clock Driver  
Functional Description  
Features  
Advanced CMOS Technology  
The ASM2P3805E is a 3.3V clock driver built using  
advanced CMOS technology. The device consists of two  
banks of drivers, each with a 1:5 fanout and its own output  
enable control. The device has a "heartbeat" monitor for  
diagnostics and PLL driving. The MON output is identical to  
all other outputs and complies with the output specifications  
in this document. The ASM2P3805E offers low capacitance  
inputs. The ASM2P3805E is designed for high speed clock  
distribution where signal quality and skew are critical. The  
ASM2P3805E also allows single point-to-point transmission  
line driving in applications such as address distribution,  
where one signal must be distributed to multiple receivers  
with low skew and high signal quality.  
Guaranteed low skew < 200pS (max)  
Very low propagation delay < 2.5nS (max)  
Very low duty cycle distortion < 270pS (max)  
Very low CMOS power levels  
Operating frequency up to 166MHz  
TTL compatible inputs and outputs  
Inputs can be driven from 3.3V or 5V components  
Two independent output banks with 3-state control  
1:5 fanout per bank  
"Heartbeat" monitor output  
VCC = 3.3V ± 0.3V  
Available in SSOP and QSOP Packages  
Block Diagram  
Pin Diagram  
OEA  
INA  
5
VCCA  
OA1  
1
2
20  
19  
OA1 – OA5  
VCCB  
OB1  
3
4
5
6
7
18  
17  
16  
15  
14  
OA2  
OB2  
OB3  
GNDB  
OB4  
OB5  
OA3  
5
INB  
OB1 – OB5  
MON  
GNDA  
OA4  
ASM2P3805E  
OEB  
OA5  
8
9
13  
GNDQ  
OEA  
INA  
MON  
OEB  
INB  
12  
11  
10  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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