Datasheet > 逻辑 > 时钟驱动器> ASM2I3805EG-20-DT

ASM2I3805EG-20-DT

更新时间： 2024-11-23 22:11:55

品牌	Logo	应用领域
ALSC		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
12页	500K
描述
3.3V CMOS Dual 1-To-5 Clock Driver

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June 2005

rev 0.2

ASM2P3805X

3.3V CMOS Dual 1-To-5 Clock Driver

Functional Description

Features

Advanced CMOS Technology

The ASM2P3805X is a 3.3V clock driver built using

advanced CMOS technology. The device consists of two

banks of drivers, each with a 1:5 fanout and its own output

enable control. The device has a "heartbeat" monitor for

diagnostics and PLL driving. The MON output is identical to

all other outputs and complies with the output specifications

in this document. The ASM2P3805X offers low capacitance

inputs. The ASM2P3805X is designed for high speed clock

distribution where signal quality and skew are critical. The

ASM2P3805X also allows single point-to-point transmission

line driving in applications such as address distribution,

where one signal must be distributed to multiple receivers

with low skew and high signal quality.

Guaranteed low skew < 200pS (max)

Very low propagation delay < 2.5nS (max)

Very low duty cycle distortion < 270pS (max)

Very low CMOS power levels

Operating frequency up to 166MHz

TTL compatible inputs and outputs

Inputs can be driven from 3.3V or 5V components

Two independent output banks with 3-state control

1:5 fanout per bank

ASM2P3805X

Where X =D for 133MHz Operation

X =E for 166MHz Operation

"Heartbeat" monitor output

V_CC= 3.3V ± 0.3V

Available in SSOP and QSOP Packages

Pin Diagram

Block Diagram

V_CCA

V_CCB

OB₁

OE_A

IN_A

OA₁

OA₂

OA₁– OA₅

OB₂

OB₃

GND_B

OB₄

OB₅

MON

OE_B

IN_B

OA₃

GND_A

OA₄

IN_B

OB₁– OB₅

MON

OA₅

OE_B

GND_Q

OE_A

IN_A

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...12

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