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ASM2I5T905AF-28TR PDF预览

ASM2I5T905AF-28TR

更新时间: 2024-09-26 06:38:07
品牌 Logo 应用领域
PULSECORE 时钟
页数 文件大小 规格书
19页 682K
描述
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

ASM2I5T905AF-28TR 技术参数

生命周期:Obsolete包装说明:0.173 INCH, ROHS COMPLIANT, TSSOP-28
Reach Compliance Code:unknown风险等级:5.84
系列:905输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G28长度:9.7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:28
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):2.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mm最小 fmax:250 MHz

ASM2I5T905AF-28TR 数据手册

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November 2006  
rev 0.2  
ASM2P5T905A  
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer  
Features  
to five single-ended outputs buffer built on advanced metal  
CMOS technology. The SDR Clock buffer fanout from a  
single or differential input to five single-ended outputs  
reduces the loading on the preceding driver and provides  
an efficient clock distribution network. The ASM2P5T905A  
can act as a translator from a differential HSTL, eHSTL,  
1.8V/2.5V LVTTL, LVEPECL or single-ended 1.8V/2.5V  
LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs.  
Selectable interface is controlled by 3 level input signals  
that may be hard-wired to appropriate high-mid-low levels.  
Multiple power and grounds reduce noise.  
Guaranteed Low Skew < 25pS (max)  
Very low duty cycle distortion  
High speed propagation delay < 2.5nS. (max)  
Up to 250MHz operation  
Very low CMOS power levels  
1.5V VDDQ for HSTL interface  
Hot insertable and Over-voltage tolerant inputs  
3 level inputs for selectable interface  
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or  
LVEPECL input interface  
Selectable differential or single-ended inputs and  
five single ended outputs  
Applications:  
2.5V Supply Voltage  
Available in TSSOP Package  
ASM2P5T905A is targeted towards Clock and signal  
distribution.  
Functional Description  
The ASM2P5T905A 2.5V single data rate (SDR) Clock  
buffer is a user-selectable single-ended or differential input  
Block Diagram  
TxS  
GL  
G
OUTPUT  
Q1  
Q2  
Q3  
Q4  
Q5  
CONTROL  
OUTPUT  
RxS  
CONTROL  
A
A/VREF  
OUTPUT  
CONTROL  
OUTPUT  
CONTROL  
OUTPUT  
CONTROL  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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