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ASM2I9940LG-32-ET PDF预览

ASM2I9940LG-32-ET

更新时间: 2024-11-24 06:38:07
品牌 Logo 应用领域
PULSECORE 时钟驱动器逻辑集成电路
页数 文件大小 规格书
13页 485K
描述
Low Voltage 1:18 Clock Distribution Chip

ASM2I9940LG-32-ET 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:7 X 7 MM, 0.80 MM PITCH, GREEN, TQFP-32Reach Compliance Code:unknown
风险等级:5.68Is Samacsys:N
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:9940
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3/e6长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:18最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):5.2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN/TIN BISMUTH
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

ASM2I9940LG-32-ET 数据手册

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April 2007  
rev 1.2  
ASM2I9940L  
Low Voltage 1:18 Clock Distribution Chip  
Features  
With low output impedance (20), in both the HIGH and  
LOW logic states, the output buffers of the ASM2I9940L  
are ideal for driving series terminated transmission lines.  
With 20output impedance the ASM2I9940L has the  
capability of driving two series terminated lines from each  
output. This gives the device an effective fanout of 1:36.  
LVPECL or LVCMOS Clock Input  
2.5V LVCMOS Outputs for Pentium II  
Microprocessor Support*  
150pS Maximum Output-to-Output Skew  
Maximum Output Frequency of 250MHz  
32 Lead LQFP & TQFP Packaging  
Dual or Single Supply Device  
The differential LVPECL inputs of the ASM2I9940L allow  
the device to interface directly with a LVPECL fanout buffer  
to build very wide clock fanout trees or to couple to a high  
frequency clock source. The LVCMOS input provides a  
more standard interface for applications requiring only a  
single clock distribution chip at relatively low frequencies. In  
addition, the two clock sources can be used to provide for a  
test clock interface as well as the primary system clock. A  
logic HIGH on the LVCMOS_CLK_Sel pin will select the  
LVCMOS level clock input. All inputs of the ASM2I9940L  
have internal pullup/pulldown resistor, so they can be left  
open if unused.  
Dual VCC Supply Voltage, 3.3V Core and 2.5V  
Output  
Single 3.3V VCC Supply Voltage for 3.3V Outputs  
Single 2.5V VCC Supply Voltage for 2.5V I/O  
Pin and Function compatible to MPC940L,  
MPC9109, CY29940 and CY29940-1  
Functional Description  
The ASM2I9940L is a 1:18 low Voltage Clock distribution  
chip with 2.5V or 3.3V LVCMOS output capabilities. The  
device features the capability to select either a differential  
LVPECL or LVCMOS compatible input. The 18 outputs are  
2.5V or 3.3V LVCMOS compatible and feature the drive  
strength to drive 50series or parallel terminated  
transmission lines. With output-to-output skews of 150pS,  
the ASM2I9940L is ideal as a clock distribution chip for the  
most demanding of Synchronous systems. The 2.5V  
outputs also make the device ideal for supplying clocks for  
a high performance microprocessor based design.  
The ASM2I9940L is a single or dual supply device. The  
device power supply offers a high degree of flexibility. The  
device can operate with a 3.3V core and 3.3V output, a  
3.3V core and 2.5V outputs as well as a 2.5V core and  
2.5V outputs. The 32-lead LQFP and TQFP Packages  
were chosen to optimize performance, board space and  
cost of the device. The 32-lead LQFP and TQFP Packages  
have a 7x7mm2 body size with conservative 0.8mm pin  
spacing.  
* Pentium II is a trademark of Intel Corporation  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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