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ASM2I9942P-32-LT PDF预览

ASM2I9942P-32-LT

更新时间: 2024-11-27 20:24:55
品牌 Logo 应用领域
PULSECORE 驱动逻辑集成电路
页数 文件大小 规格书
10页 433K
描述
Low Skew Clock Driver, 9942 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 0.80 MM PITCH, LQFP-32

ASM2I9942P-32-LT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:7 X 7 MM, 0.80 MM PITCH, LQFP-32Reach Compliance Code:unknown
风险等级:5.73Is Samacsys:N
其他特性:IT CAN ALSO OPERATE WITH 3.3V SUPPLY系列:9942
输入调节:DIFFERENTIALJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:18最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4.3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ASM2I9942P-32-LT 数据手册

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May 2005  
rev 0.3  
ASM2I9942P  
Low Voltage 1:18 Clock Distribution Chip  
Features  
With low output impedance (12), in both the HIGH and  
LOW logic states, the output buffers of the ASM2I9942P  
are ideal for driving series terminated transmission lines.  
With an output impedance of 12, the ASM2I9942P can  
drive two series terminated transmission lines from each  
output. This capability gives the ASM2I9942P an effective  
fanout of 1:36. The ASM2I9942P provides enough copies  
of low skew clocks for most high performance synchronous  
systems.  
ƒ
ƒ
LVPECL Clock Input  
2.5V LVCMOS Outputs for Pentium IITM*  
Microprocessor Support  
ƒ
200pS Maximum Targeted Output–to–Output  
Skew  
ƒ
ƒ
ƒ
ƒ
Maximum Output Frequency of 250MHz @3.3 VCC  
32–Lead LQFP and TQFP Packaging  
Single 3.3V or 2.5V Supply  
The differential LVPECL inputs of the ASM2I9942P allow  
the device to interface directly with a LVPECL fanout buffer  
to build very wide clock fanout trees or to couple to a high  
frequency clock source. The OE pins will place the outputs  
into a high impedance state. The OE pin has an internal  
pullup resistor.  
Pin and Function compatible with MPC942P  
Functional Description  
The ASM2I9942P is a 1:18 low voltage clock distribution  
chip with 2.5V or 3.3V LVCMOS output capabilities. The  
device is offered in two versions; the ASM2I9942C has an  
LVCMOS input clock while the ASM2I9942P has a  
LVPECL input clock. The 18 outputs are 2.5V or 3.3V  
LVCMOS compatible and feature the drive strength to drive  
50series or parallel terminated transmission lines. With  
output-to-output skews of 200pS, the ASM2I9942P is ideal  
as a clock distribution chip for the most demanding of  
synchronous systems. The 2.5V outputs also make the  
device ideal for supplying clocks for a high performance  
The ASM2I9942P is a single supply device. The VCC power  
pins require either 2.5V or 3.3V. The 32 lead LQFP and  
TQFP package is chosen to optimize performance, board  
space and cost of the device. The 32–lead LQFP and  
TQFP have a 7x7mm2 body size with conservative 0.8mm  
pin spacing.  
Pentium IITM microprocessor based design.  
* Pentium II is a trademark of Intel Corporation  
Block Diagram  
Table 1. Function Table  
Q0  
OE  
Output  
PECL_CLK  
PECL_CLK  
Q1-Q16  
0
1
HIGH IMPEDANCE  
OUTPUTS ENABLED  
Q17  
OE  
(Int. Pullup)  
Alliance Semiconductor  
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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