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ASM2I99446-32-LR

更新时间： 2024-11-27 20:28:35
品牌 Logo 应用领域
PULSECORE 驱动逻辑集成电路
页数 文件大小 规格书
14页 575K
描述
Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32

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ASM2I99446-32-LR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：7 X 7 MM, LQFP-32Reach Compliance Code：unknown
风险等级：5.76Is Samacsys：N
其他特性：IT CAN ALSO OPERATE WITH 3.3V SUPPLY系列：99446
输入调节：MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e0长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：32
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：5.6 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.35 ns
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

ASM2I99446-32-LR 数据手册

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July 2005  
rev 0.4  
ASM2I99446  
2.5V and 3.3V LVCMOS Clock Distribution Buffer  
Features  
is specified for the extended temperature range of -40°C to  
85°C.  
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Configurable 10 outputs LVCMOS clock  
distribution buffer  
Compatible to single, dual and mixed 3.3V/2.5V  
Voltage supply  
Wide range output clock frequency up to 250MHz  
Designed for mid-range to high-performance  
telecom, networking and computer applications  
Supports applications requiring clock redundancy  
Max. output skew of 200pS (150pS within one  
bank)  
Selectable output configurations per output bank  
Tristatable outputs  
32 lead LQFP & TQFP Packages  
Pin and Function compatible with MPC9446  
Ambient operating temperature range of  
-40 to 85°C  
The ASM2I99446 is a full static fanout buffer design  
supporting clock frequencies up to 250MHz. The signals  
are generated and retimed on-chip to ensure minimal skew  
between the three output banks. Two independent  
LVCMOS compatible clock inputs are available. This  
feature supports redundant clock sources or the addition of  
a test clock into the system design. Each of the three  
output banks can be individually supplied by 2.5V or 3.3V  
supporting mixed voltage applications. The FSELx pins  
choose between division of the input reference frequency  
by one or two. The frequency divider can be set individually  
for each of the three output banks. The ASM2I99446 can  
be reset and the outputs are disabled by deasserting the  
MR/OE pin (logic high state). Asserting MR/OE will enable  
the outputs.  
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All inputs accept LVCMOS signals while the outputs  
provide LVCMOS compatible levels with the capability to  
drive terminated 50Ω transmission lines. Please consult the  
ASM2I99456 specification for a 1:10 mixed voltage buffer  
with LVPECL compatible inputs. For series terminated  
transmission lines, each of the ASM2I99446 outputs can  
drive one or two traces giving the devices an effective  
fanout of 1:20. The device is packaged in a 7x7mm2  
32-lead LQFP and TQFP Packages.  
Functional Description  
The ASM2I99446 is a 2.5V and 3.3V compatible 1:10 clock  
distribution buffer designed for low-voltage mid-range to  
high-performance telecom, networking and computing  
applications. Both 3.3V, 2.5V and dual supply voltages are  
supported for mixed-voltage applications. The ASM2I99446  
offers 10 low-skew outputs and 2 selectable inputs for clock  
redundancy. The outputs are configurable and support 1:1  
and 1:2 output to input frequency ratios. The ASM2I99446  
Alliance Semiconductor  
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com  
Notice: The information in this document is subject to change without notice.  
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