5秒后页面跳转
捷配首页

Datasheet > ASM2I99446-32-ET
ASM2I99446-32-ET PDF预览

ASM2I99446-32-ET

更新时间： 2024-11-24 20:28:35
品牌 Logo 应用领域
PULSECORE 驱动逻辑集成电路
页数 文件大小 规格书
14页 575K
描述
Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, TQFP-32

阅读下载

中文翻译

获取价格

ASM2I99446-32-ET 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：7 X 7 MM, TQFP-32Reach Compliance Code：unknown
风险等级：5.76Is Samacsys：N
其他特性：IT CAN ALSO OPERATE WITH 3.3V SUPPLY系列：99446
输入调节：MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e0长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：32
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：5.6 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.35 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

ASM2I99446-32-ET 数据手册

 浏览型号ASM2I99446-32-ET的Datasheet PDF文件第2页浏览型号ASM2I99446-32-ET的Datasheet PDF文件第3页浏览型号ASM2I99446-32-ET的Datasheet PDF文件第4页浏览型号ASM2I99446-32-ET的Datasheet PDF文件第5页浏览型号ASM2I99446-32-ET的Datasheet PDF文件第6页浏览型号ASM2I99446-32-ET的Datasheet PDF文件第7页 
July 2005  
rev 0.4  
ASM2I99446  
2.5V and 3.3V LVCMOS Clock Distribution Buffer  
Features  
is specified for the extended temperature range of -40°C to  
85°C.  
ƒ
Configurable 10 outputs LVCMOS clock  
distribution buffer  
Compatible to single, dual and mixed 3.3V/2.5V  
Voltage supply  
Wide range output clock frequency up to 250MHz  
Designed for mid-range to high-performance  
telecom, networking and computer applications  
Supports applications requiring clock redundancy  
Max. output skew of 200pS (150pS within one  
bank)  
Selectable output configurations per output bank  
Tristatable outputs  
32 lead LQFP & TQFP Packages  
Pin and Function compatible with MPC9446  
Ambient operating temperature range of  
-40 to 85°C  
The ASM2I99446 is a full static fanout buffer design  
supporting clock frequencies up to 250MHz. The signals  
are generated and retimed on-chip to ensure minimal skew  
between the three output banks. Two independent  
LVCMOS compatible clock inputs are available. This  
feature supports redundant clock sources or the addition of  
a test clock into the system design. Each of the three  
output banks can be individually supplied by 2.5V or 3.3V  
supporting mixed voltage applications. The FSELx pins  
choose between division of the input reference frequency  
by one or two. The frequency divider can be set individually  
for each of the three output banks. The ASM2I99446 can  
be reset and the outputs are disabled by deasserting the  
MR/OE pin (logic high state). Asserting MR/OE will enable  
the outputs.  
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
All inputs accept LVCMOS signals while the outputs  
provide LVCMOS compatible levels with the capability to  
drive terminated 50Ω transmission lines. Please consult the  
ASM2I99456 specification for a 1:10 mixed voltage buffer  
with LVPECL compatible inputs. For series terminated  
transmission lines, each of the ASM2I99446 outputs can  
drive one or two traces giving the devices an effective  
fanout of 1:20. The device is packaged in a 7x7mm2  
32-lead LQFP and TQFP Packages.  
Functional Description  
The ASM2I99446 is a 2.5V and 3.3V compatible 1:10 clock  
distribution buffer designed for low-voltage mid-range to  
high-performance telecom, networking and computing  
applications. Both 3.3V, 2.5V and dual supply voltages are  
supported for mixed-voltage applications. The ASM2I99446  
offers 10 low-skew outputs and 2 selectable inputs for clock  
redundancy. The outputs are configurable and support 1:1  
and 1:2 output to input frequency ratios. The ASM2I99446  
Alliance Semiconductor  
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com  
Notice: The information in this document is subject to change without notice.  
1234567...14

中文翻译

下载PDF

与ASM2I99446-32-ET相关器件

型号 品牌 获取价格 描述 数据表
ASM2I99446-32-LR ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer
ASM2I99446-32-LR PULSECORE

获取价格

 		Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X
ASM2I99446-32-LT ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer
ASM2I99446-32-LT PULSECORE

获取价格

 		Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X
ASM2I99446G-32-ER ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer
ASM2I99446G-32-ET ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer
ASM2I99446G-32-ET PULSECORE

获取价格

 		Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X
ASM2I99446G-32-LR ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer
ASM2I99446G-32-LR PULSECORE

获取价格

 		Low Skew Clock Driver, 99446 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X
ASM2I99446G-32-LT ALSC

获取价格

 		2.5V and 3.3V LVCMOS Clock Distribution Buffer

与ASM2I99446-32-ET相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证