January 2006
rev 0.2
ASM2P3805E
3.3V CMOS Dual 1-To-5 Clock Driver
Functional Description
Features
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Advanced CMOS Technology
The ASM2P3805E is a 3.3V clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The ASM2P3805E offers low capacitance
inputs. The ASM2P3805E is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805E also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Guaranteed low skew < 200pS (max)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
VCC = 3.3V ± 0.3V
Available in SSOP and QSOP Packages
Block Diagram
Pin Diagram
OEA
INA
5
VCCA
OA1
1
2
20
19
OA1 – OA5
VCCB
OB1
3
4
5
6
7
18
17
16
15
14
OA2
OB2
OB3
GNDB
OB4
OB5
OA3
5
INB
OB1 – OB5
MON
GNDA
OA4
ASM2P3805E
OEB
OA5
8
9
13
GNDQ
OEA
INA
MON
OEB
INB
11
10
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.