Datasheet > 存储 > SRAM> AS7C33512PFD36A-133TQCN

AS7C33512PFD36A-133TQCN

更新时间： 2024-10-27 23:00:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

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AS7C33512PFD32A

AS7C33512PFD36A

Signal descriptions

Description

CLK

I/O Properties

CLOCK

SYNC

Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and when OE is active.

A,A0,A1

DQ[a,b,c,d]

I/O

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,

ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE0

SYNC

Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when

ADSC is active or when CE0 and ADSP are active.

CE1, CE2

ADSP

ADSC

ADV

SYNC

Address strobe processor. Asserted low to load a new address or to enter standby mode.

Address strobe controller. Asserted low to load a new address or to enter standby mode.

Advance. Asserted low to continue burst read/write.

Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]

control write enable.

GWE

BWE

SYNC

Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.

Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of

BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,

the cycle is a read cycle.

BW[a,b,c,d]

SYNC

ASYNC

STATIC

Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.

Selects Burst mode. When tied to V_DDor left floating, device follows interleaved Burst order. When

driven Low, device follows linear Burst order. This signal is internally pulled High.

LBO

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I_SB2. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I_SB2is guaranteed after the time t_ZZIis met. After entering SNOOZE MODE, all inputs except ZZ is

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during t_PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

2/10/05, v 1.3

Alliance Semiconductor

5 of 19

1 2 3 456 7 8...19

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与AS7C33512PFD36A-133TQCN相关器件

型号	品牌	获取价格	描述	数据表
AS7C33512PFD36A-133TQI	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-133TQIN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQC	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQCN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQI	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQIN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-200BC	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD36A-200BI	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD36A-200TQC	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFD36A-200TQI	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

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