Datasheet > 存储 > SRAM> AS7C33512PFD36A-133TQCN

AS7C33512PFD36A-133TQCN

更新时间： 2024-10-27 23:00:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS7C33512PFD36A-133TQCN 数据手册

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第1页

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第2页

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第3页

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第5页

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第6页

浏览型号AS7C33512PFD36A-133TQCN的Datasheet PDF文件第7页

AS7C33512PFD32A

AS7C33512PFD36A

Functional description

The AS7C33512PFD32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device

organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Fast cycle times of 6/7.5 ns with clock access times (t_CD) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip enable (CE)

inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor

address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address

strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved

count sequence. With LBO driven low, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/

36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE

and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented

internally to the next burst address if BWn and ADV are sampled low. This device operates in double-cycle deselect feature during read

cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are

as follows:

• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33512PFD32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or

3.3V. These devices are available in a 100-pin TQFP package.

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

Test conditions

V_IN= 0V

Min

Max

Unit

C_IN

C_I/O

V_OUT= 0V

* Guaranteed not tested

TQFP thermal resistance

Description

Conditions

Symbol

θ_JA

Typical

Units

°C/W

1–layer

4–layer

Thermal resistance

(junction to ambient)¹

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

θ_JA

Thermal resistance

(junction to top of case)¹

θ_JC

°C/W

1 This parameter is sampled

2/10/05, v 1.3

Alliance Semiconductor

4 of 19

1 2 345 6 7...19

中文翻译

下载PDF

与AS7C33512PFD36A-133TQCN相关器件

型号	品牌	获取价格	描述	数据表
AS7C33512PFD36A-133TQI	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-133TQIN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQC	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQCN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQI	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-166TQIN	ALSC	获取价格	3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD36A-200BC	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD36A-200BI	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD36A-200TQC	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFD36A-200TQI	ALSC	获取价格	Standard SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

与AS7C33512PFD36A-133TQCN相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

12
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

12
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

39
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

46

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C33512PFD36A-133TQCN

AS7C33512PFD36A-133TQCN 数据手册

与AS7C33512PFD36A-133TQCN相关器件

与AS7C33512PFD36A-133TQCN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C33512PFD36A-133TQCN

AS7C33512PFD36A-133TQCN 数据手册

与AS7C33512PFD36A-133TQCN相关器件

与AS7C33512PFD36A-133TQCN相关文章

您还可以找

您在本页遇到什么问题？