February 2005
AS7C33512PFD32A
AS7C33512PFD36A
®
3.3V 512K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 524,288 words × 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.4/3.8 ns
• Fast OE access time: 3.4/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
DDQ
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
Q0
Burst logic
CLR
512K × 32/36
Q1
Memory
array
19
17
19
19
D
CE
CLK
Q
A[18:0]
Address
register
36/32
36/32
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
registers
4
BWa
CLK
CE0
CE1
OE
Output
registers
CLK
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
36/32
DQ[a:d]
OE
Selection guide
-166
6
-133
7.5
133
3.8
275
80
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
166
3.4
300
90
MHz
ns
mA
mA
mA
Maximum CMOS standby current (DC)
60
60
2/10/05, v 1.3
Alliance Semiconductor
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