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AS7C33256NTF36A-75TQCN PDF预览

AS7C33256NTF36A-75TQCN

更新时间: 2024-11-04 20:22:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
18页 427K
描述
ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33256NTF36A-75TQCN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.52
最长访问时间:7.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:9437184 bit
内存集成电路类型:ZBT SRAM内存宽度:36
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX36
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):245
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

AS7C33256NTF36A-75TQCN 数据手册

 浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第2页浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第3页浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第4页浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第5页浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第6页浏览型号AS7C33256NTF36A-75TQCN的Datasheet PDF文件第7页 
AS7C33256NTF32A  
AS7C33256NTF36A  
November 2004  
®
3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Organization: 262,144 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
• 3.3 core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• 30 mW typical standby power  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
Logic Block Diagram  
18  
18  
Q
A[17:0]  
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
256K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
Output  
Buffer  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection Guide  
-75  
8.5  
7.5  
300  
120  
30  
-85  
10  
-10  
12  
Units  
ns  
Minimum cycle time  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.5  
280  
110  
30  
10  
ns  
240  
100  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
11/8/04, v. 1.1  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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