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AS7C33256PFD18B-133TQC PDF预览

AS7C33256PFD18B-133TQC

更新时间: 2024-11-04 20:30:51
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
19页 536K
描述
Standard SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33256PFD18B-133TQC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.38
Is Samacsys:N最长访问时间:4 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:4718592 bit内存集成电路类型:STANDARD SRAM
内存宽度:18功能数量:1
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX18封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AS7C33256PFD18B-133TQC 数据手册

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AS7C33256PFD18B  
February 2005  
®
3.3V 256K × 18 pipeline burst synchronous SRAM  
Features  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• 3.3V core power supply  
• Organization: 262,144 words × 18 bits  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.0/3.5/4.0 ns  
• Fast OE access time: 3.0/3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Double-cycle deselect  
• 2.5V or 3.3V I/O operation with separate V  
DDQ  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
Burst logic  
256K × 18  
Memory  
array  
ADSC  
ADSP  
CLR  
18  
Q
D
A[17:0]  
Address  
18  
CS  
16  
18  
register  
CLK  
18  
2
18  
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
CLK  
BWE  
BW  
D
Q
DQa  
Byte Write  
a
registers  
CLK  
CE0  
CE1  
OE  
Output  
registers  
D
Q
Q
Input  
registers  
Enable  
register  
CE2  
CE  
CLK  
CLK  
CLK  
D
Enable  
delay  
register  
Power  
down  
ZZ  
CLK  
OE  
18  
DQ [a,b]  
Selection guide  
–200  
5
–166  
–133  
7.5  
133  
4
Units  
Minimum cycle time  
6
ns  
MHz  
ns  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.0  
375  
130  
30  
166  
3.5  
350  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
30  
1/31/05; v.1.2  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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