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AS7C33256PFD32A-133TQCN PDF预览

AS7C33256PFD32A-133TQCN

更新时间: 2024-11-04 20:20:15
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
20页 527K
描述
Standard SRAM, 256KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33256PFD32A-133TQCN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.39
Is Samacsys:N最长访问时间:4 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:32功能数量:1
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX32封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):245认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

AS7C33256PFD32A-133TQCN 数据手册

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December 2004  
AS7C33256PFD32A  
AS7C33256PFD36A  
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM  
Features  
• Organization: 262,144 words x 32 or 36 bits  
• Fast clock speeds to 166 MHz  
• Fast clock to data access: 3.5/4.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Dual-cycle deselect  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• 3.3V core power supply  
• Asynchronous output enable control  
• Available in100-pin TQFP  
• 2.5V or 3.3V I/O operation with separate V  
DDQ  
Logic block diagram  
LBO  
CLK  
CLK  
CE  
ADV  
Burst logic  
ADSC  
CLR  
256K × 32/36  
Memory  
array  
18  
ADSP  
2
2
18  
16  
18  
D
CE  
CLK  
Q
A
[17:0]  
Address  
register  
36/32  
36/32  
BWE  
GWE  
d
D
Q
DQ  
d
Byte write  
BW  
registers  
CLK  
D
Q
DQ  
c
BW  
c
Byte write  
registers  
CLK  
D
Q
DQ  
b
BW  
b
Byte write  
registers  
CLK  
D
Q
DQ  
a
4
BW  
a
Byte write  
registers  
CLK  
D
CE0  
CE1  
CE2  
OE  
Q
Q
Output  
Input  
Enable  
register  
registers  
registers  
CE  
CLK  
CLK  
CLK  
D
Enable  
Power  
down  
delay  
ZZ  
register  
CLK  
36/32  
DQ[a:d]  
OE  
Selection guide  
–166  
6
–133  
7.5  
133  
4
Units  
Minimum cycle time  
ns  
MHz  
ns  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.5  
475  
130  
30  
425  
100  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
12/1/04, v.1.2  
Alliance Semiconductor  
P. 1 of 20  
Copyright ©Alliance Semiconductor. All rights reserved.  

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