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AS7C33256NTD32A-133BC PDF预览

AS7C33256NTD32A-133BC

更新时间: 2024-11-30 20:56:55
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
12页 324K
描述
ZBT SRAM, 256KX32, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

AS7C33256NTD32A-133BC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.64
最长访问时间:10 nsJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:8388608 bit内存集成电路类型:ZBT SRAM
内存宽度:32功能数量:1
端子数量:119字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX32封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:2.4 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AS7C33256NTD32A-133BC 数据手册

 浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第2页浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第3页浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第4页浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第5页浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第6页浏览型号AS7C33256NTD32A-133BC的Datasheet PDF文件第7页 
March 2002  
AS7C33256NTD32A  
AS7C33256NTD36A  
&
1
TM  
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Features  
• Organization: 262,144 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Available in 100-pin TQFP and 119-ball BGA package  
• Byte write enables  
™1  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.0/3.5/3.8/4/5 ns  
• Fast OE access time: 3.5/3.8/4/5 ns  
• Fully synchronous operation  
• “Flow-through” or “pipelined” mode  
• Asynchronous output enable control  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3 core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• 30 mW typical standby power  
• Self-timed write cycles  
DDQ  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
1. NTD is a trademark of Alliance Semiconductor Corporation.  
Logic block diagram  
18  
18  
Q
D Address  
register  
Burst logic  
A[17:0]  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/W  
BWa  
BWb  
BWc  
Control  
logic  
CLK  
BWd  
256K x 32/36  
SRAM  
ADV / LD  
FT  
CLK  
LBO  
Array  
ZZ  
36/32  
36/32  
Data  
Register  
CLK  
DATA [a:d]  
Q
D
Input  
36/32  
36/32  
36/32  
CLK  
CEN  
CLK  
Output  
Register  
OE  
36/32  
DATA [a:d]  
OE  
Selection guide  
-166  
6
-150  
6.7  
-133  
7.5  
133  
4
-100  
10  
Units  
Minimum cycle time  
ns  
MHz  
ns  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.0/3.51  
150  
3.8  
100  
5
475  
425  
110  
30  
400  
100  
30  
300  
90  
mA  
mA  
mA  
Maximum standby current  
130  
Maximum CMOS standby current (DC)  
30  
30  
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.  
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