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AS7C251MNTD32A-200TQCN PDF预览

AS7C251MNTD32A-200TQCN

更新时间： 2024-01-11 17:35:37
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 436K
描述
2.5V 1M x 32/36 Pipelined SRAM with NTD

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AS7C251MNTD32A-200TQCN 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.38
Is Samacsys：N最长访问时间：3.2 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：33554432 bit内存集成电路类型：ZBT SRAM
内存宽度：32功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX32封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：245认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

AS7C251MNTD32A-200TQCN 数据手册

 浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第3页浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第4页浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第5页浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第7页浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第8页浏览型号AS7C251MNTD32A-200TQCN的Datasheet PDF文件第9页 
AS7C251MNTD32A  
AS7C251MNTD36A  
®
Burst order  
Interleaved burst order (LBO = 1)  
A1 A0 A1 A0 A1 A0 A1 A0  
Linear burst order (LBO = 0)  
A1 A0 A1 A0 A1 A0 A1 A0  
Starting address  
First increment  
0 0  
0 1  
0 1  
0 0  
1 1  
1 0  
1 0  
1 1  
0 0  
0 1  
1 1  
1 0  
0 1  
0 0  
Starting Address  
First increment  
0 0  
0 1  
0 1  
1 0  
1 1  
0 0  
1 0  
1 1  
0 0  
0 1  
1 1  
0 0  
0 1  
1 0  
Second increment 1 0  
Third increment 1 1  
Second increment 1 0  
Third increment  
1 1  
Synchronous truth table[5,6,7,8,9,11]  
Address  
CE0 CE1 CE2 ADV/LD R/W  
BWn  
OE CEN source  
CLK  
Operation  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
Q
Notes  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA  
NA  
NA  
NA  
L to H  
L to H  
L to H  
L to H  
DESELECT Cycle  
DESELECT Cycle  
DESELECT Cycle  
X
H
X
H
X
H
X
H
CONTINUE DESELECT Cycle  
READ Cycle (Begin Burst)  
READ Cycle (Continue Burst)  
1
External L to H  
Next L to H  
X
L
X
L
L
Q
1,10  
2
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z  
X
L
X
L
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10  
External L to H  
WRITE CYCLE (Begin Burst)  
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)  
1,3,10  
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3  
1,2,3,  
X
X
X
H
X
H
X
X
L
Next L to H WRITE ABORT (Continue Burst)  
High-Z  
10  
X
X
X
X
X
X
H
Current L to H  
INHIBIT CLOCK  
-
4
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or  
more byte write signals are LOW.  
Notes:  
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial  
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.  
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a  
WRITE command is given, but no operation is performed.  
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE  
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.  
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will  
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.  
5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins); BWc enables WRITEs to byte “c” (DQc pins); BWd  
enables WRITEs to byte “d” (DQd pins).  
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.  
7 Wait states are inserted by setting CEN HIGH.  
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.  
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.  
10 The address counter is incremented for all CONTINUE BURST cycles.  
11 ZZ pin is always Low in this truth table.  
1/17/05, V 1.2  
Alliance Semiconductor  
P. 6 of 18  
1...3456789...18

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