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AS7C251MNTD32A-200TQCN PDF预览

AS7C251MNTD32A-200TQCN

更新时间: 2024-01-01 17:55:08
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 436K
描述
2.5V 1M x 32/36 Pipelined SRAM with NTD

AS7C251MNTD32A-200TQCN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.38
Is Samacsys:N最长访问时间:3.2 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:33554432 bit内存集成电路类型:ZBT SRAM
内存宽度:32功能数量:1
端子数量:100字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX32封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):245认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

AS7C251MNTD32A-200TQCN 数据手册

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AS7C251MNTD32A  
AS7C251MNTD36A  
®
Signal descriptions  
Signal  
CLK  
I/O Properties Description  
I
I
I
CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.  
CEN  
SYNC  
SYNC  
SYNC  
Clock enable. When de-asserted high, the clock input signal is masked.  
Address. Sampled when all chip enables are active and ADV/LD is asserted.  
Data. Driven as output when the chip is enabled and OE is active.  
A, A0, A1  
DQ[a,b,c,d] I/O  
CE0, CE1,  
CE2  
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.  
Are ignored when ADV/LD is high.  
I
SYNC  
SYNC  
SYNC  
SYNC  
Advance or Load. When sampled high, the internal burst address counter will increment in  
the order defined by the LBO input value. When low, a new address is loaded.  
ADV/LD  
R/W  
I
I
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE  
operation. Is ignored when ADV/LD is high.  
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE  
command and BURST WRITE.  
BW[a,b,c,d]  
OE  
I
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
STATIC  
LBO  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
ZZ  
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
NC  
-
No connect  
Snooze Mode  
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of  
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.  
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.  
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ  
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.  
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting  
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE  
MODE.  
1/17/05, V 1.2  
Alliance Semiconductor  
P. 5 of 18  

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