Datasheet > AS7C251MNTD36A-167BCN

AS7C251MNTD36A-167BCN

更新时间： 2022-12-02 00:06:51

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
22页	453K
描述
ZBT SRAM, 1MX36, 7.5ns, CMOS, PBGA165, LEAD-FREE, BGA-165

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April 2004

AS7C251MNTD32A

AS7C251MNTD36A

2.5V 1M × 32/36 SRAM with NTD^TM

Features

• Common data inputs and data outputs

• Organization: 1,048,576 words × 32 or 36 bits

• NTD^™1architecture for efficient bus operation

• Fast clock speeds to 200 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.1/3.4/3.8 ns

• Fast OE access time: 3.1/3.4/3.8 ns

• Asynchronous output enable control

• Available in 100-pin TQFP and 165-ball BGA packages

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Fully synchronous operation

• Flow-through or pipelined mode

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Boundary scan using IEEE 1149.1 JTAG function

1. NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-

marks mentioned in this document are the property of their respective owners.

Logic block diagram

A[19:0]

Address

Burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

Control

logic

CLK

BWb

BWc

BWd

ADV / LD

1M x 32/36

SRAM

LBO

CLK

Array

32/36

DQ[a,b,c,d]

Data

Input

32/36

CLK

32/36

CLK

CEN

CLK

Output

32/36

DQ[a,b,c,d]

Selection guide

-200

-167

-133

7.5

Units

Minimum cycle time

Maximum pipelined clock frequency

Maximum pipelined clock access time

Maximum operating current

200

3.1

400

120

167

3.4

350

110

133

3.8

MHz

325

100

Maximum standby current

Maximum CMOS standby current (DC)

4/26/04, V 1.0

Alliance Semiconductor

P. 1 of 22

12 3 4 5 6 7...22

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