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AS6UA5128-55BC PDF预览

AS6UA5128-55BC

更新时间: 2024-11-06 19:36:19
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
9页 118K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, CSP, FBGA-48/36

AS6UA5128-55BC 数据手册

 浏览型号AS6UA5128-55BC的Datasheet PDF文件第2页浏览型号AS6UA5128-55BC的Datasheet PDF文件第3页浏览型号AS6UA5128-55BC的Datasheet PDF文件第4页浏览型号AS6UA5128-55BC的Datasheet PDF文件第5页浏览型号AS6UA5128-55BC的Datasheet PDF文件第6页浏览型号AS6UA5128-55BC的Datasheet PDF文件第7页 
May 2001  
AS6UA5128  
®
2.3V to 3.6V 512K×8 Intelliwatt low-power CMOS SRAM  
Features  
• AS6UA5128  
- 41 µW max at 2.7V  
- 28 µW max at 2.3V  
• 1.5V data retention  
• Equal access and cycle times  
• Easy memory expansion with CS, OE inputs  
• Smallest footprint packages  
- 36(48)-ball FBGA  
• ESD protection 2000 volts  
• Latch-up current 200 mA  
• Intelliwatt™ active power circuitry  
• Industrial and commercial temperature ranges available  
• Organization: 524,288 words × 8 bits  
• 2.7V to 3.6V at 55 ns  
• 2.3V to 2.7V at 70 ns  
• Low power consumption: ACTIVE  
- 144 mW at 3.6V and 55 ns  
- 68 mW at 2.7V and 70 ns  
• Low power consumption: STANDBY  
- 72 µW max at 3.6V  
Pin arrangement  
Logic block diagram  
V
CC  
36(48)-CSP/BGA Package (shading indicates no ball)  
GND  
1
2
3
4
5
6
Input buffer  
A
B
C
D
E
F
G
H
A0  
A1  
A2  
NC  
WE  
NC  
A3  
A4  
A5  
A6  
A7  
A8  
I/O5  
I/O6  
VSS  
VCC  
I/O7  
I/O8  
A9  
I/O1  
I/O2  
VCC  
VSS  
I/O3  
I/O4  
A14  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
I/O8  
I/O1  
512K  
×
8
Array  
A18  
CS  
A17  
A16  
A12  
(4,194,304)  
OE  
A15  
A13  
A10  
A11  
WE  
OE  
CS  
Column decoder  
Control  
circuit  
Selection guide  
V
CC Range  
Power Dissipation  
Typ2  
(V)  
3.0  
Max  
Speed  
(ns)  
55  
Operating (ICC)  
Standby (ISB1  
)
Min  
(V)  
2.7  
2.3  
Product  
AS6UA5128  
AS6UA5128  
(V)  
3.6  
2.7  
Max (mA)  
Max (µA)  
2
1
20  
15  
2.5  
70  
5/25/01; v.1.1  
Alliance Semiconductor  
P. 1 of 9  
Copyright ©Alliance Semiconductor. All rights reserved.  

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