Datasheet > 存储 > DRAM> AS4LC4M16S0-75TC

AS4LC4M16S0-75TC

更新时间： 2024-02-22 20:44:14

品牌	Logo	应用领域
ALSC		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
24页	548K
描述
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

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AS4LC4M16S0-75TC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2,
针数：	54	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.28	Is Samacsys：	N
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PDSO-G54
长度：	22.22 mm	内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	54	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	自我刷新：	YES
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

AS4LC4M16S0-75TC 数据手册

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AS4LC4M16S0

AS4LC16M4S0

Device operation

Command

Pin settings

Description

The following sequence must be performed prior to normal

operation.

1. Apply power, start clock, and assert CKE and DQM high. All other

signals are NOP.

2. After power-up, pause for a minimum of 200µs.

CKE/ DQM = high; all others NOP.

Power up

3. Precharge both banks.

4. Perform Mode Register Set command to initialize mode register.

5. Perform a minimum of 8 auto refresh cycles to stabilize internal

circuitry.

(Steps 4 and 5 may be interchanged.)

The mode register stores the user selected opcode for the SDRAM

operating modes. The CAS latency, burst length, burst type, test mode

and other vendor specific functions are selected/ programmed during

the Mode Register Set command cycle. The default setting of the

mode register is not defined after power-up. The power-up and mode

Refer to the Mode Register Set table and timing for details.

CS = RAS = CAS = WE = low;

A0~A11 = opcode

Mode register set

The SDRAM performs a “no operation” (NOP) when RAS, CAS, and

WE = high. Since the NOP performs no operation, it may be used as

a wait state in performing normal SDRAM functions. The SDRAM is

deselected when CS is high. CS high disables the command decoder

such that RAS, CAS, WE and address inputs are ignored. Device

deselection is also considered a NOP.

Device deselect and no

operation

CS = high

The SDRAM is configured with four internal banks. Use the Bank

Activate command to select a row in one of the idle banks. Initiate

a read or write operation after t_RCD(min) from the time of bank

activation.

CS = RAS = low; CAS = WE =

high; A0~A10 = row address;

BA0~BA1 = bank select

Bank activation

Burst read

Use the Burst Read command to access a consecutive burst of data

from an active row in an active bank. Burst read can be initiated on

any column address of an active row. The burst length, sequence and

latency are determined by the mode register setting. The first output

data appears after the CAS latency from the read command. The

output goes into a high impedance state at the end of the burst

(BL = 1,2,4,8) unless a new burst read is initiated to form a gapless

output data stream. Terminate the burst with a burst stop command,

precharge command to the same bank or another burst read/ write.

CS = CAS = A10 = low; RAS =

WE = high; BA0~BA1 = bank

select, A0~A8 = column

address; (A9 = don’t care for

8M×8; A8,A9 = don’t care for

4M×16)

Use the Burst Write command to write data into the SDRAM on

CS = CAS = WE = A10 = low; consecutive clock cycles to adjacent column addresses. The burst

RAS = high; A0~A9 = column length and addressing mode is determined by the mode register

address; (A9 = don’t care for opcode. Input the initial write address in the same clock cycle as the

8M×8; A8,A9 = don’t care for Burst Write command. Terminate the burst with a burst stop

Burst write

4M×16)

command, precharge command to the same bank or another burst

read/ write.

Use DQM to mask input and output data on a cycle-by-cycle basis. It

disables the output buffers in a read operation and masks input data in

a write operation. The output data is invalid 2 clocks after DQM

assertion (2 clock latency). Input data is masked on the same clock as

DQM assertion (0 clock latency).

UDQM/ LDQM (×16),

DQM (×8) operation

ALLIANCE SEMICONDUCTOR

7/ 5/ 00

1...7 8 91011 12 13...24

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