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AS4LC4M16S0-75TC PDF预览

AS4LC4M16S0-75TC

更新时间: 2024-01-21 01:01:35
品牌 Logo 应用领域
ALSC 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
24页 548K
描述
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

AS4LC4M16S0-75TC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.28Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G54
长度:22.22 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

AS4LC4M16S0-75TC 数据手册

 浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第4页浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第5页浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第6页浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第8页浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第9页浏览型号AS4LC4M16S0-75TC的Datasheet PDF文件第10页 
AS4LC8M8S0  
AS4LC4M16S0  
®
I
specifications and conditions  
DD  
(0° C T 70° C, V , V  
= +3.3V ± 0.3V)  
A
DD DDQ  
Max  
–8  
Parameter  
Operating current: active mode; burst = 2; READ or WRITE;  
RC = tRC(min); CAS latency = 3  
Symbol  
IDD1  
–75  
115  
–10F/ 10 Units Notes  
95  
2
95  
2
mA  
mA  
mA  
mA  
mA  
4, 5  
4,5  
t
Standby current: power-down mode; all banks idle;  
CKE = low  
IDD2  
IDD3  
IDD4  
IDD5  
2
Standby current: active mode; CKE = high; CS# = high; all  
banks active after tRCD met; no accesses in progress  
45  
35  
35  
4, 5  
4,5  
Operating current: burst mode; continuous burst; READ or  
WRITE; all banks active; CAS latency = 3  
140  
210  
130  
210  
120  
190  
tRFC = tRFC(min);  
4, 5  
CL = 3  
Auto refresh current: CKE = high;  
CS# = high  
tRFC = 15.625ms;  
CL = 3  
IDD6  
IDD7  
50  
1
50  
1
40  
1
mA  
mA  
4,5  
4,5  
Self-refresh current: CKE 0.2V  
Notes  
1
2
3
4
5
I
specifications are tested after proper initialization of the device.  
DD  
I
is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.  
DD  
I
tests have V = 0V and V = 3V.  
IL IH  
current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.  
DD  
I
DD  
Address transitions average one transition every two clock cycles.  
7/ 5/ 00  
ALLIANCE SEMICONDUCTOR  
7

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