Datasheet > AN-90

AN-90

更新时间： 2022-11-25 11:11:44

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
7页	212K
描述
74C Family Characteristics

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AN-90 数据手册

voltages. To obtain actual power consumption find the nor-

malized power for a particular V_CCand frequency, then mul-

tiply by C_PD+ C_L.

plex and has many nodes charging and discharging at vari-

ous rates, all of the effects can be easily lumped into one

easy to use term, C_PD

Calculation of transient power due to load capacitance is a

little more complex since each output is switched at one half

the rate of the previous output: Taking this into account the

complete expression for power consumption is:

AN006021-9

FIGURE 6. Normalized Typical Power

Consumption vs Frequency

This reduces to:

P_TOTAL(C_PD+ C_L) V_CC2 f + I_LV_CC

As an example let’s find the total power consumption for an

From the data sheet C_PD90 pF and I_L0.05 µA. Using

Figure 6 total power is then:

MM74C00 operating at f 100 kHz, V_CC10V and C_L50

pF. From the curve, normalized power per gate equals 10

µW/pF. From the data sheet C_PD12 pF; therefore, actual

power per gate is:

This demonstrates that with more complex devices the con-

cept of C_PDgreatly simplifies the calculation of total power

consumption. It becomes an easy task to compute power for

different voltages and frequencies by use of Figure 6 and the

equations above.

Up to this point the discussion of power consumption has

been limited to simple gate functions. Power consumption

for an MSI function is more complex but the same technique

just derived applies. To demonstrate the technique let’s com-

pute the total power consumption of a MM74C161, four bit

PROPAGATION DELAY

Propagation delay for all 54C/74C devices is guaranteed

with a load of 50 pF and input rise and fall times of 20 ns. A

50 pF load was chosen, instead of 15 pF as in the 4000 se-

ries, because it is representative of loads commonly seen in

CMOS systems. A good rule of thumb, in designing with

CMOS, is to assume 10 pF of interwiring capacitance. Oper-

ating at the specified propagation delay would allow 5 pF

binary counter, at V_CC10V, f 1 MHz and C_L50 pF on

each output.

The no load power is still given by P (no load)

C_PDV_CC2 f.

This demonstrates the usefulness of the concept of the inter-

nal capacitance, C_PD. Even though the circuit is very com-

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1 2 345 6 7

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