www.fairchildsemi.com
AN-9050
FDMF6704 Power Loss Calculation
YoungSub Jeong MCCC Application Engineering
FDMF6704 are optimized for a 5 V power rail in computing
applications. Both pins are normally connected to each
other in an application. The VSWH pin is the switch node
of Synchronous Buck converter. It is connected to the
internal HS FET source and LS FET drain. As a point of
view of a module product, VIN, VCIN and VDRV are
inputs and VSWH is output. The module power loss and
efficiency are defined by formulas as below.
Introduction
The FDMF6704 DrMOS MCM (Multi Chip Module)
product has HS and LS FETs and a gate driver all contained
within a single module. The design has been optimized for
Synchronous Buck applications. The switching and
conduction loss of each HS FET, LS FET and gate driver
are critical for system and application design. Generally it is
hard to get measurement of each internal loss because of its
MCM structure. Instead of measuring each power loss
elements, expression of module power loss have been used
to show MCM product power related performance. Module
power loss is defined to be all power losses dissipated by
DrMOS module itself. It includes all HS FET, LS FET and
gate driver power losses. Using this approach, a system
designer can easily estimate total power loss of the system,
and do easy and convenient predictions of design related
application performance. This application note explains
basic theory of module power loss, and how to use the
module power loss calculation tool. It is easy and
z
Module Power Loss
= Module input power – Module output power
= (Pin + Pcin&Pdrv) – Psw [W]
z
Module Efficiency
= Module output power / Module input power
= Psw / (Pin + Pcin&Pdrv) * 100 [%]
convenient to use the power loss calculator when the system
designer does a particular application design.
Power Loss of DrMOS
Figure 1 shows a typical Synchronous Buck application
circuit using an FDMF6704 DrMOS product. The
Figure 1. Typical Application Circuit of FDMF6704
application schematic is based on a Fairchild Semiconductor
FDMF6704 evaluation board which is used for datasheet
characterization testing. The circuit includes all components
in a Sync Buck converter except for the PWM controller.
The PWM control function is accomplished by external
voltage compensation loop using a pulse generator and a PC
automation program. All passive components and layout,
such as input caps, output caps, output inductor and boot
cap, are optimized for DrMOS products.
The primary power loss elements in a Sync Buck converter
are the switching devices and the output inductor. Silicon
conduction and switching loss represent the largest element
of the power loss in a typical Sync Buck converter.
Normally inductor power loss is added to silicon loss to
determine the system total performance. Key points of good
inductor design include saturation current (adequate to
handle peak transients), low DCR, core type, low noise and
thermal characteristics. With a properly chosen inductor,
module power loss is essentially independent of inductor
power loss. Since we want to focus on silicon loss tradeoffs,
we will use module power loss as our figure of merit to
compare MCM designs.
Power loss sense point pins of FDMF6704 are VIN, VCIN,
VDRV and VSWH. VIN is an input pin for main DC/DC
power converting. It is connected to the internal HS FET
drain. The current into VIN is related to HS FET switching
and conduction losses. Its voltage level is typically 12 V in
computing application. The VCIN pin is connected to the
VCC of internal gate drive logic. The VDRV pin is used for
HS and LS FET gate driving voltage. VCIN & VDRV of
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
www.fairchildsemi.com
5秒后页面跳转
压敏电阻器在直流电路中的过压保护应用探讨
电感耐压值及其与电感大小的关系
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
DS1307资料解析：特性、引脚说明、替代推荐
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
