SHARC+ Dual-Core
DSP with Arm Cortex-A5
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
Preliminary Technical Data
SYSTEM FEATURES
MEMORY
Dual-enhanced SHARC+ floating-point cores
High performance SHARC+ cores (up to 1 GHz each)
Up to 5 Mb (640 kB) L1 SRAM memory per core with parity
(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed-point support
Byte, short word, word, and long word addressability
Arm Cortex-A5 core
Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16
32 kB L1 instruction and data caches with parity
256 kB L2 cache with parity
Large on-chip Level 2 (L2) SRAM with ECC protection, up to
2 MB
One Level 3 (L3) interface providing 16-bit interface to
DDR3/ DDR3L SDRAM devices
ADDITIONAL FEATURES
ADSP-2156x pin-compatible package options
Enhanced FIR and IIR accelerators running up to 1 GHz
Security and protection
Cryptographic hardware accelerators
Fast secure boot with IP protection
Support for Arm TrustZone
Powerful DMA system with 8 MemDMAs
On-chip memory protection
APPLICATIONS
Integrated safety features
17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),
RoHS compliant
Automotive: audio amplifier, head unit, ANC/RNC, rear seat
entertainment, digital cockpit, ADAS
Consumer: AVRs, mixing consoles, microphone arrays,
conferencing systems
CORE 1
CORE 2
PERIPHERALS
SYSTEM CONTROL
SECURITY AND PROTECTION
SRU
DAI0
8× PRECISION CLOCK
GENERATORS
SYSTEM PROTECTION UNIT (SPU)
S
S
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
(UP TO 1 GHz)
(UP TO 1 GHz)
ASRC
8× PAIRS
FULL SPORT
0-7
DRU
DAI1
ACCELERATORS
FIR 4× IIR
ACCELERATORS
FIR 4× IIR
ENCRYPTION/DECRYPTION
2× S/PDIF Rx/Tx
UP TO
40
FAULT MANAGEMENT UNIT (FMU)
L1 SRAM (PARITY)
L1 SRAM (PARITY)
2× 4-CHANNEL
PDM MIC INPUT
®
®
Arm TrustZone SECURITY
DUAL CRC (WITH MemDMA)
WATCHDOGS
(UP TO (UP TO
1 GHz) 1 GHz)
(UP TO (UP TO
1 GHz) 1 GHz)
5 Mb (640 kB)
SRAM/CACHE
5 Mb (640 kB)
SRAM/CACHE
6× I2C
2× LINK PORTS
OTP MEMORY
2× SPI + 2× QUAD SPI +
1× OCTAL SPI
THERMAL MONITOR UNIT (TMU)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
4× UARTs
1× EPPI
PROGRAM FLOW
SYS EVENT CORE 0 (GIC)
G
P
I
SYS EVENT CORES 1-2 (SEC)
TRIGGER ROUTING (TRU)
16× TIMERS + 1× COUNTER
2× CAN FD
UP TO
135
O
CORE 0
L3 MEMORY
INTERFACE
SYSTEM
L2 MEMORY
2× EMAC
CLOCK, RESET, AND POWER
L2 CACHE
256 kB (PARITY)
CLOCK GENERATION UNIT (CGU)
1× USB 2.0 HS OTG
CONTROLLER
SRAM
(ECC)
DDR3/DDR3L
L1 CACHE (PARITY)
32 kB L1 I-CACHE
32 kB L1 D-CACHE
CLOCK DISTRIBUTION
UNIT (CDU)
UP TO 2 MB
32x CORE FLAGS I/O
MLB 3-PIN
RESET CONTROL UNIT (RCU)
BOOT ROM
16
6
Arm®
DYNAMIC POWER MANAGEMENT
(DPM)
MLB 6-PIN
DATA
Cortex®-A5
(UP TO 1 GHz)
HADC (8-CHANNEL, 12-BIT)
DEBUG UNIT
UP TO
8
TM
®
Arm CoreSight
SYSTEM WATCHPOINT UNIT
(SWU)
Figure 1. ADSP-SC594 (Full-Featured Model) Processor Block Diagram
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