PRELIMINARY TECHNICAL DATA
TigerSHARC®
a
DSP Microcomputer
ADSP-TS101S
Preliminary Technical Data
KEY FEATURES
KEY BENEFITS
Operates at 250 MHz, 4.0 ns Instruction Cycle Rate
Has 6M Bits of Internal—On-Chip—SRAM Memory
Comes in Either a 19؋
19 mm (484-Ball) or 27؋
27 mm
(625-Ball) PBGA Package
Provides High-Performance Static Superscalar DSP
Operations, Optimized for Telecommunications
Infrastructure and Other Large, Demanding
Multiprocessor DSP Applications
Contains Dual Computation Blocks—Each Containing
an ALU, a Multiplier, a Shifter, and a Register File
Contains Dual Integer ALUs, providing Data Addressing
and Pointer Manipulation
Includes an External Port, Four Link Ports, SDRAM
Controller, Programmable Flag Pins, Two Timers, and
Timer Expired Pin for System Integration
Includes 1149.1 IEEE Compliant JTAG Test Access Port
for On-Chip Emulation
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1 and Table 2)
Includes DMA Controller Support on 14 DMA Channels,
Performing Low-Overhead DMA Transfers Between
Internal Memory, External Memory, Memory-Mapped
Peripherals, Link Ports, Host Processors, and Other
(Multiprocessor) DSPs
Eases DSP Programming Through Extremely Flexible
Instruction Set and High-Level-Language Friendly
DSP Architecture
Has On-Chip Arbitration for Glueless Multiprocessing
With up to Eight TigerSHARC DSPs on a Common Bus
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
DATA ADDRESS GENERATION
INTERNAL MEMORY
6
JTAG PORT
SDRAM CONTROLLER
EXTERNAL PORT
MEMORY MEMORY MEMORY
32
32
INTEGER
J ALU
INTEGER
K ALU
M0
M1
M2
64K X 32
64K X 32
64K X 32
ADDR
FETCH
32X32
32X32
IAB
A
D
A
D
A
D
ALU
MULTIPLIER
32
M0 ADDR
M0 DATA
X
MULTIPROCESSOR
INTERFACE
128
REGISTER
FILE
32x32
32
HOST INTERFACE
INPUT FIFO
32
ADDR
64
M1 ADDR
M1 DATA
128 128
DAB
128
DATA
OUTPUT BUFFER
OUTPUT FIFO
32
DAB
M2 ADDR
M2 DATA
128
CNTRL
128 128
CLUSTER BUS
ARBITOR
I/O ADDRESS
32
Y
I/O PROCESSOR
REGISTER
FILE
32x32
3
8
3
8
L0
DMA
CONTROLLER
LINK PORT
CONTROLLER
MULTIPLIER
ALU
L1
L2
L3
DMA ADDRESS
DMA DATA
LINK
PORTS
32 128
128
3
8
LINK DATA
CONTROL/
STATUS/
TCB'S
CONTROL/
STATUS/
BUFFERS
®
3
8
SHIFTER
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
REV. PrE
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
assumes no obligation regarding future manufacturing unless otherwise Tel:781/329-4700
agreed to in writing. Fax:781/326-8703
www.analog.com
© Analog Devices, Inc., 2002